Samsung Electronics Co., Ltd.

Kyungsoo Ha

Kyungryun Kim

Changkyo Lee

Jinhoon Jang

Kiseok Oh

Dongkeon Lee

Kiheung Kim

Sungchul Park

Taeyoung Oh

Hyojin Jung

Sanguhn Cha

Junhyung Kim

Jongcheol Kim

Hohyun Shin

Hyunsung Shin

Hyeran Kim

Sungyong Cho

JunHyung Kim

Sungju Lee

Hangyun Jung

A semiconductor memory device includes a memory cell array, a row hammer management circuit and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The row hammer management circuit counts the number of instances of access of each of the memory cell rows, such as in response to the receipt of an active command, to store the counted values in count cells of each of the memory cell rows as count data and, in response to a first command, initiates an internal read-update-write operation to read the count data, to update the read count data, and to write the updated count data in the count cells. The control logic circuit may performs an internal write operation to write the updated count data in the count cells during a second write time interval that is smaller than a first write time interval associated with a normal write operation.

Semiconductor memory device and methods of operation

A semiconductor memory device includes a memory cell array, a data input/output (I/O) buffer, an I/O gating circuit and a control logic circuit. The memory cell array includes a plurality of sub array blocks arranged in a first direction and a second direction. The data I/O buffer exchanges user data with a memory controller through I/O pads. The I/O gating circuit is connected to the data I/O buffer through data buses and connected to the memory cell array through data I/O lines, and programs mapping relationship between the sub array blocks and the I/O pads, based on a mapping control signal such that uncorrectable errors that are detected by an error correction code engine in the memory controller are reduced. The control logic circuit generates the mapping control signal based on identifier information indicating a type of a central processing unit of the memory controller.

Semiconductor memory devices

A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The scrubbing control circuit generates scrubbing addresses for performing a scrubbing operation on a first memory cell row based on refresh row addresses for refreshing the memory cell rows. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection and correction operation on a plurality of sub-pages in the first memory cell row to count a number of error occurrences during a first interval and determines a sub operation in a second interval in the scrubbing operation based on the number of error occurrences in the first memory cell row.

Semiconductor memory devices and methods of operating semiconductor memory devices

A signal transmitting and receiving apparatus including: a first on-die termination circuit connected to a first pin through which a first signal is transmitted or received and, when enabled, the first on-die termination circuit is configured to provide a first termination resistance to a signal line connected to the first pin; a second on-die termination circuit connected to a second pin through which a second signal is transmitted or received and, when enabled, the second on-die termination circuit is configured to provide a second termination resistance to a signal line connected to the second pin; and an on-die termination control circuit configured to independently control an enable time and a disable time of each of the first on-die termination circuit and the second on-die termination circuit.

Apparatus for transmitting and receiving a signal, a method of operating the same, a memory device, and a method of operating the memory device

A voltage generator includes a charge pump circuit including a first charge pump having a plurality of first pumping capacitors, and a second charge pump having a plurality of second pumping capacitors having a capacitance different from a capacitance of each of the plurality of first pumping capacitors. The charge pump circuit is configured to supply a power supply voltage to a power mesh. The voltage generator further includes a controller configured to output a control signal based on a target level of the power supply voltage, and an oscillator configured to output a clock signal to the charge pump circuit. The oscillator outputs the clock signal to one of the first charge pump and the second charge pump based on the control signal.

Voltage generator and semiconductor device including the same

A semiconductor memory device includes a memory cell array, a sense amplifier circuit and a random code generator. The memory cell array is divided into a plurality of sub array blocks arranged in a first direction and a second direction crossing the first direction. The sense amplifier circuit is arranged in the second direction with respect to the memory cell array, and includes a plurality of input/output (I/O) sense amplifiers. The random code generator generates a random code which is randomly determined based on a power stabilizing signal and an anti-fuse flag signal. A second group of I/O sense amplifiers selected from among a first group of I/O sense amplifiers performs a data I/O operation by data scrambling data bits of main data. The first group of I/O sense amplifiers correspond to a first group of sub array blocks accessed by an access address.

Semiconductor memory device and a method of operating the semiconductor memory device

Growing community of inventors

Suwon-si, South Korea

Kyungsoo Ha