Samsung Electronics Co., Ltd.

Kyungjoong Joo

Won-Seok Jung

Changseok Kang

Seungwoo Paek

Inseok Yang

Jihye Kim

Jaehan Lee

Youngok Kim

Provided are semiconductor devices and methods of fabricating the same. The semiconductor devices may include a substrate with a cell region and a peripheral region, a gate stack including gates stacked on the cell region of the substrate. At least one edge portion of the gate stack may have a staircase structure. The semiconductor devices may also include a channel that extend through the gate stack and is enclosed by a memory layer and at least two dummy patterns on the substrate. The at least two dummy patterns may be spaced apart from the gate stack and may be spaced apart from each other.

Semiconductor devices having dummy patterns and methods of fabricating the same

A semiconductor device includes a substrate, a stack structure, peripheral gate structures and residual spacers. The substrate includes a cell array region and a peripheral circuit region. The stack structure is disposed on the cell array region, having electrodes and insulating layers alternately stacked. The peripheral gate structures are disposed on the peripheral circuit region, being spaced apart from each other in one direction and having a peripheral gate pattern disposed on the substrate, and a peripheral gate spacer disposed on a sidewall of the peripheral gate pattern. The residual spacers are disposed on sidewalls of the peripheral gate structures, having a sacrificial pattern and an insulating pattern that are stacked. The insulating pattern includes substantially the same material as the insulating layers of the stack structure.

Semiconductor device and method of fabricating the same

Semiconductor device and method for fabricating the same

A semiconductor memory device may include stacks arranged in a first direction and vertical channel structures provided through the stacks. Each of the stacks may include gate electrodes and insulating layers alternately stacked on a substrate. Each of the vertical channel structures may include a semiconductor pattern connected to the substrate and a vertical channel pattern connected to the semiconductor pattern. Each of the semiconductor patterns may have a recessed sidewall, and the semiconductor patterns may have minimum widths different from each other.

Semiconductor memory devices and methods of fabricating the same

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Suwon-si, South Korea

Kyungjoong Joo