Samsung Electronics Co., Ltd.

Kyungjae Park

Jonghyun Park

Sunyoung Kim

Bora Lee

Sooyong Lee

Jongho Lim

Bongsoo Kang

Jongsu Park

Cheol Ryou

Moojoon Shin

Seorim Moon

Leeeun Ku

Yuna Lee

A vertical type non-volatile memory device includes a substrate having a cell array area of a block unit and an extension area, a vertical contact disposed in the extension area, a plurality of vertical channel structures provided on the substrate in the cell array area, a plurality of dummy channel structures provided on the substrate in the extension area, and a plurality of gate electrode layers and a plurality of interlayer insulation layers stacked alternately on the substrate. In an electrode pad connected to the vertical contact, dummy channel structures are disposed at both sides of the vertical contact and a horizontal cross-sectional surface of each of the plurality of dummy channel structures has a shape which is longer in one direction.

Vertical type non-volatile memory device and method of manufacturing the same

A semiconductor device includes a peripheral circuit region including a first substrate and circuit devices on the first substrate, a memory cell region including a second substrate on the first substrate, a horizontal conductive layer on the second substrate, gate electrodes stacked on the horizontal conductive layer in a first direction perpendicular to an upper surface of the second substrate and spaced apart from each other, and channel structures extending in gate electrodes in the first direction, each of the channel structures including a channel layer in physical contact with the horizontal conductive layer, and a through wiring region including a through contact plug extending in the first direction and electrically connecting the memory cell region to the peripheral circuit region, an insulating region bordering the through contact plug, and dummy channel structures partially extending into the insulating region in the first direction.

Semiconductor device including dummy channels and through wiring structure

A method of manufacturing a semiconductor device includes forming a lower structure including first repetitive patterns, and forming an upper structure including forming second repetitive patterns to correspond to each of the first repetitive patterns on the lower structure, and the forming second repetitive patterns includes preparing a design layout for the second repetitive patterns, forming a first correction layout including corrected second repetitive patterns by performing optical proximity correction (OPC) on the design layout, forming a second correction layout by performing position correction on the first correction layout to move a position of the corrected second repetitive patterns to correspond to a changed position of the first repetitive patterns according to physical deformation of the lower structure, manufacturing a mask using the second correction layout, and patterning a photoresist layer using the mask.

Method of designing a mask and method of manufacturing a semiconductor device using the same

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Suwon-si, South Korea

Kyungjae Park