Samsung Electronics Co., Ltd.

Kyungin Choi

Jinbum Kim

Haejun Yu

Seunghun Lee

Seung Hun Lee

Dahye Kim

Jaemun Kim

Sangmoon Lee

Gyeom Kim

Taegon Kim

Ilgyou Shin

Kihyun Hwang

Hyunchul Song

Taehyeon Kim

Keun Hwi Cho

Seokhoon Kim

Sunjung Kim

Changhwa Kim

Seong Hoon Jeong

Yoonhae Kim

Yuichiro Sasaki

Jaeyoung Park

Hongshik Shin

Sunghyun Choi

Dohyoung Kim

Yong-Suk Tak

Bonyoung Koo

Hyojin Kim

Hwichan Jun

Kwang-Yong Yang

Inchan Hwang

Myungil Kang

Ah-Young Cheon

Jaejong Han

Dongwoo Kim

Sungmin Kim

Chang Woo Sohn

Dohee Kim

Jiho Yoo

Seon-Bae Kim

Ki-Hyung Ko

Dongmyoung Kim

Jaeran Jang

Youngmoon Choi

Soonwook Jung

A semiconductor device includes first and second channels, first and second gate structures, first and second source/drain layers, first and second fin spacers, and first and second etch stop patterns. The first channels are disposed vertically on a first region of a substrate. The second channels are disposed vertically on a second region of the substrate. The first gate structure is formed on the first region and covers the first channels. The second gate structure is formed on the second region and covers the second channels. The first and second source/drain layers contact the first and second channels, respectively. The first and second fin spacers contact sidewalls and upper surfaces of the first and second source/drain layers, respectively. The first and second etch stop patterns are formed on the first and second fin spacers, respectively, and do not contact the first and second source/drain layers, respectively.

Semiconductor devices including source/drain layers and methods of manufacturing the same

An integrated circuit device includes: a fin-type active area protruding from a substrate, extending in a first direction parallel to an upper surface of the substrate, and including a first semiconductor material; an isolation layer arranged on the substrate and covering a lower portion of a sidewall of the fin-type active area, the isolation layer including an insulation liner conformally arranged on the lower portion of the sidewall of the fin-type active area, and an insulation filling layer on the insulation liner; a capping layer surrounding an upper surface and the sidewall of the fin-type active area, including a second semiconductor material different from the first semiconductor material, and with the capping layer having an upper surface, a sidewall, and a facet surface between the upper surface and the sidewall; and a gate structure arranged on the capping layer and extending in a second direction perpendicular to the first direction.

Integrated circuit devices and methods of manufacturing the same

A semiconductor device includes an active pattern provided on a substrate, a source/drain pattern provided on the active pattern, a channel pattern configured to be connected to the source/drain pattern, a gate electrode configured to be extended in a first direction and to cross the channel pattern, and a first spacer provided on a side surface of the gate electrode. The first spacer includes a fence portion provided on a side surface of the active pattern and below the source/drain pattern. The source/drain pattern includes a body portion and a neck portion between the body portion and the active pattern. The body portion includes a crystalline surface configured to be slantingly extended from the neck portion. The crystalline surface is configured to be spaced apart from an uppermost portion of the fence portion.

Semiconductor device and method of fabricating the same

An integrated circuit device is provided and includes: a fin-type active region extending in a first horizontal direction on a substrate, a channel region on the fin-type active region, a gate line surrounding the channel region on the fin-type active region and extending in a second horizontal direction crossing the first horizontal direction, an insulating spacer covering a sidewall of the gate line, a source/drain region connected to the channel region on the fin-type active region and including a first portion facing the sidewall of the gate line with the insulating spacer therebetween, an air gap between the insulating spacer and the first portion of the source/drain region, and an insulating liner including a portion in contact with the source/drain region and a portion defining a size of the air gap. A method of manufacturing the integrated circuit device is further provided.

Integrated circuit device and method of manufacturing the same

A semiconductor device includes an active pattern on a substrate, a pair of source/drain patterns on the active pattern, a channel pattern between the pair of source/drain patterns, the channel pattern including semiconductor patterns stacked to be spaced apart from each other, and a gate electrode crossing the channel pattern and extending in a first direction. One of the pair of source/drain patterns includes a first semiconductor layer and a second semiconductor layer thereon. The first semiconductor layer is in contact with a first semiconductor pattern, which is one of the stacked semiconductor patterns. The largest widths of the first semiconductor pattern, the first semiconductor layer, and the second semiconductor layer in the first direction are a first width, a second width, a third width, respectively, and the second width is larger than the first width and smaller than the third width.

Semiconductor device having a liner layer and method of fabricating the same

A semiconductor device includes: a first active pattern on a substrate and including a first active fin and a second active fin; a device isolation layer defining the first active pattern; a gate electrode crossing the first active pattern; a first source/drain pattern and a second source/drain pattern on the first active fin and the second active fin, respectively; an inner fin spacer between the first and second source/drain patterns; and a buffer layer between the first and second active fins, wherein the inner fin spacer includes: a first inner spacer portion contacting the first source/drain pattern; a second inner spacer portion contacting the second source/drain pattern; and an inner extended portion extending from the first and second inner spacer portions, wherein the inner extended portion is between the first and second active fins, wherein the buffer layer has a dielectric constant higher than that of the inner fin spacer.

Method of forming a static random-access memory (SRAM) cell with fin field effect transistors

A semiconductor device is disclosed. The semiconductor device may include a semiconductor substrate including a protruding active pattern, a first gate pattern provided on the active pattern and extended to cross the active pattern, a first capping pattern provided on a top surface of the first gate pattern, the first capping pattern having a top surface, a side surface, and a rounded edge, and a first insulating pattern covering the side surface and the edge of the first capping pattern. A thickness of the first insulating pattern on the edge of the first capping pattern is different from a thickness of the first insulating pattern on outer side surfaces of the spacer patterns.

Semiconductor device including a capping pattern

An integrated circuit device includes a plurality of gate structures each including a gate line extending on a fin-type active region and insulation spacers on sidewalls of the gate line; a source/drain contact between first and second gate structures, and having opposing sides that are asymmetric in the first horizontal direction; and an insulation liner on sidewalls of the source/drain contact. The source/drain contact includes a lower contact portion and an upper contact portion having a horizontal extension that extends on an upper corner of the first gate structure, the insulation liner includes a first local region between the upper corner and the horizontal extension and a second local region that is farther from the substrate than the first local region, and a thickness of the first local region is greater than that of the second local region.

Integrated circuit device

An active pattern structure includes a lower active pattern protruding from an upper surface of a substrate in a vertical direction substantially perpendicular to an upper surface of the substrate, a buffer structure on the lower active pattern, at least a portion of which may include aluminum silicon oxide, and an upper active pattern on the buffer structure.

Active pattern structure and semiconductor device including the same

A semiconductor device includes an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern connected to the source/drain pattern, the channel pattern including semiconductor patterns stacked and spaced apart from each other, a gate electrode extending across the channel pattern, and inner spacers between the gate electrode and the source/drain pattern. The semiconductor patterns include stacked first and second semiconductor patterns. The gate electrode includes first and second portions, which are sequentially stacked between the substrate and the first and second semiconductor patterns, respectively. The inner spacers include first and second air gaps, between the first and second portions of the gate electrode and the source/drain pattern. The largest width of the first air gap is larger than that of the second air gap.

Semiconductor device having air gap between gate electrode and source/drain pattern

An integrated circuit device includes: a fin-type active region extending in a first horizontal direction on a substrate, a channel region on the fin-type active region, a gate line surrounding the channel region on the fin-type active region and extending in a second horizontal direction crossing the first horizontal direction, an insulating spacer covering a sidewall of the gate line, a source/drain region connected to the channel region on the fin-type active region and including a first portion facing the sidewall of the gate line with the insulating spacer therebetween, an air gap between the insulating spacer and the first portion of the source/drain region, and an insulating liner including a portion in contact with the source/drain region and a portion defining a size of the air gap.

A semiconductor device includes a substrate including a first active pattern and a second active pattern, a device isolation layer filling a first trench between the first and second active patterns, the device isolation layer including a silicon oxide layer doped with helium, a helium concentration of the device isolation layer being higher than a helium concentration of the first and second active patterns, and a gate electrode crossing the first and second active patterns.

Method of fabricating a semiconductor device

A method includes forming an active pattern on a substrate, the active pattern comprising first semiconductor patterns and second semiconductor patterns, which are alternately stacked, forming a capping pattern on a top surface and a sidewall of the active pattern, performing a deposition process on the capping pattern to form an insulating layer, and forming a sacrificial gate pattern intersecting the active pattern on the insulating layer. The capping pattern has a crystalline structure and is in physical contact with sidewalls of the first semiconductor patterns and sidewalls of the second semiconductor patterns.

Semiconductor device

Growing community of inventors

Seoul, South Korea

Kyungin Choi