Skhynix Inc.

Korea Advanced Institute of Science and Technology

Kyunghyun Kim

SeongHwan Cho

Hyukjin Lee

Jino Seo

A semiconductor memory device includes a cell array including a plurality of memory cells connected between a first bit line and a source line; a computation control circuit configured to control a first bit line current between the first bit line and the source line during a computation operation; and an output circuit including a first computation capacitor whose charge amount is changed according to the first bit line current during the computation operation, wherein an amount of charge that flows between the first bit line and the source line during the computation operation depends on both data stored in a memory cell among the plurality of memory cells according to a first data and a voltage of a word line connected to the memory cell provided according to a second data.

Semiconductor memory device performing a multiplication and accumulation operation

A semiconductor device includes a memory cell array including a plurality of memory cells coupled between a multiplicity of word lines and one or more bit lines; and an operation circuit configured to perform a multiplication and accumulation (MAC) operation with one or more first multi-bit data provided from the one or more bit lines and one or more second multi-bit data, wherein a plurality of memory cells coupled to a bit line store a plurality of bits included in a corresponding one of the one or more first multi-bit data, and wherein the memory cell array sequentially provides the plurality of bits included in the corresponding first multi-bit data to the operation circuit.

Growing community of inventors

Daejeon, South Korea

Kyunghyun Kim