Samsung Electronics Co., Ltd.

Lg Electronics Inc.

Soulbrain Co., Ltd.

Kyunghyun Kim

Se-Ho Cha

Yongsun Ko

Daehong Eom

ChangSup Mun

Jun-Youl Yang

Hoon Hee Han

Sukhun Choi

Sejoon You

Kwangsu Kim

Byoungmoon Yoon

Yong-Hoon Son

Kyounghwan Kim

Phil Ouk Nam

Kijong Park

Jihoon Jeong

Hankyu Cho

Sang Won Bae

Yeon-Sil Sohn

Jinuk Lee

Jaewan Park

Taeheon Kim

Junghun Lim

Kwangchul Park

Seonghwan Park

Chanjin Jeong

Yanghwa Lee

Byeongju Kim

Wonbong Jung

JongHeun Lim

Hyunsuk Choi

Kihyun Hwang

Sechung Oh

Byoungkeun Son

Jangeun Lee

JinGyun Kim

Junho Jeong

Daehyun Jang

Hyunha Kim

Sunghae Lee

Sanghoon Jeong

Chadong Yeo

Jeongsoo Lee

Jin-I Lee

Young-taek Hong

Jongmun Choi

Seongsoo Lee

Kyungnam Park

Siyoung Kim

Changsup Mun

Jae Jin Shin

Sunghwan Kim

Jinwoo Lee

Sunil Shim

Hongseok Kim

Sangcheon Kim

Dougyong Sung

Kyungtae Nam

Sungho Jang

Youngdo Kim

Hyo-Jung Kim

Inseak Hwang

Sangjun Hong

Sangki Nam

Sang-Jun Lee

Ana Kim

Keonyoung Kim

Mongsup Lee

Seokhoon Kang

Daewon Kang

Minkwang Lee

Yongseog Jeon

Chansoo Kang

Yoonho Son

Young Taek Hong

Hakju Kim

KyungTae Nam

Youngju Choi

Changsoon Lim

Jonghun Pi

Sungwon Cho

Jongkyo Jeong

Jiwoon Lim

Myoungwoo Lee

Younsok Choi

Myungjung Pyo

JaHyung Han

Yonseog Jeon

Donhee Lee

Younseon Wang

Junyoul Yang

Yongsik Chung

Seungcheol Chae

Choongkee Seong

Kyunjin Lee

Sunjoong Song

Poonggi Jung

Seonjung Kim

Byoung Jae Park

Jin-l Lee

A wet etching method includes: providing a structure including an etching target film into a process bath containing a first etching solution having a first phosphoric acid concentration; performing a first etching process for etching the etching target film with the first etching solution in the process bath; providing a second etching solution having a second phosphoric acid concentration different from the first phosphoric acid concentration by changing a phosphoric acid concentration in the first etching solution; performing a second etching process for etching the etching target film with the second etching solution in the process bath; providing a third etching solution having a third phosphoric acid concentration different from the first and second phosphoric acid concentrations by changing a phosphoric acid concentration in the second etching solution; and performing a third etching process for etching the etching target film with the third etching solution in the process bath.

Wet etching method and method of fabricating semiconductor device by using the same

A plasma sensor module may include an upper substrate, a lower substrate, at least one probe and a printed circuit board (PCB). The upper substrate may be configured to be exposed to plasma. The lower substrate may contact a lower surface of the upper substrate. The lower substrate may have a thickness that is thicker than a thickness of the upper substrate. The probe may be in the lower substrate. The PCB may be in the lower substrate. The PCB may be configured to apply an alternating current to the probe to detect a density of the plasma. Thus, the structural strength of the plasma sensor module may have improved structural strength.

Plasma sensor module

An apparatus includes first and second VI sensors, an optical sensor, and an arcing detector. The first VI sensor is disposed in a power filter or on a power supply line connected to a heater disposed in a lower electrode of a process chamber in which a plasma process is performed. The first VI sensor senses a harmonic generated from a first power supply supplying power to the lower electrode and outputs a first signal. The optical sensor senses an intensity of light generated from the process chamber and outputs a second signal. The second VI sensor is disposed on a power supply line connected to an upper electrode and senses a harmonic generated from a second power supply supplying power to the upper electrode and outputs a third signal. The arcing detector determines whether arcing occurs based on one or more of the first, second, and third signals.

Apparatus for arcing diagnosis, plasma process equipment including the same, and arcing diagnosis method

An electronic device, rear plate, and method of forming the rear plate are disclosed. The electronic device includes a housing including a front plate, the rear plate facing an opposite direction to the front plate, and a side structure surrounding a space formed between the front plate and the rear plate, and a display. The rear plate includes a glass plate and decorative member, the decorative member including a first base plate, a second base plate, a first molding pattern disposed on the first base plate and including a 3-dimensional pattern, a first adhesive layer between the first molding pattern layer and the second base plate, wherein an index of refraction of the first adhesive layer is different from an index of refraction of the first molding pattern, and a shielding printing layer.

Electronic device including rear plate and method for forming the same

An electronic device and ornamental member for the same are disclosed herein. The electronic devices includes a housing, a front plate disposed on one surface of the housing, and a rear plate disposed on a rear surface of the housing, wherein one of the plates includes the ornamental member, which includes: a base film attached to one surface of a transparent plate and configured to at least partially transmit light, an ultra-violet (UV) molding layer formed on a surface of the base film, and a plurality of refractive layers sequentially stacked on a surface of the UV molding layer, wherein at least one of the plurality of refractive layers is formed to have a different refractive index and a different surface area from a remainder of the refractive layers.

Member and electronic device including the same

A semiconductor memory device includes a stack structure comprising horizontal electrodes sequentially stacked on a substrate including a cell array region and an extension region and horizontal insulating layers between the horizontal electrodes. The semiconductor memory device may further include vertical structures that penetrate the stack structure, a first one of the vertical structures being on the cell array region and a second one of the vertical structures being on the extension region. Each of the vertical structures includes a channel layer, and a tunneling insulating layer, a charge storage layer and a blocking insulating layer which are sequentially stacked on a sidewall of the channel layer. The charge storage layer of the first vertical structure includes charge storage patterns spaced apart from each other in a direction perpendicular to a top surface of the substrate with the horizontal insulating layers interposed therebetween. The charge storage layer of the second vertical structure extends along sidewalls of the horizontal electrodes and sidewalls of the horizontal insulating layers.

Semiconductor memory device and method of manufacturing the same

A plasma etching apparatus includes an etching chamber and at least one processor. The etching chamber is configured to support a target therein. The at least one processor is configured to: determine a process condition for plasma etching the target before execution of a plasma etching process; and control an aspect of the chamber according to the process condition. The process condition includes a unit etching time over which the plasma etching process is to be continuously performed.

Method and apparatus for plasma etching

A semiconductor memory device includes insulating patterns and gate patterns alternately stacked on a substrate, a channel structure that intersects the insulating patterns and the gate patterns and connected to the substrate, a charge storage structure between the channel structure and the gate patterns, and a contact structure on the substrate at a side of the insulating patterns and the gate patterns. One of the gate patterns includes a first barrier pattern between a first insulating pattern of the insulating patterns and a second insulating pattern of the insulating patterns adjacent the first insulating pattern in a first direction perpendicular to a main surface of the substrate, the first barrier pattern defining a concave region between a first portion of the first barrier pattern extending along the first insulating pattern and a second portion extending along the second insulating pattern, and a metal pattern in the concave region.

Semiconductor memory device

Disclosed are a method of wet etching and a method of fabricating a semiconductor device. The wet etching method includes providing a wafer in a process bath and an etchant is accommodated, supplying the process bath with a primary etchant to control a concentration of a specific material in the etchant, supplying the process bath with a first additive to increase the concentration of the specific material in the etchant, and supplying the process bath with a second additive to suppress a defect caused by an increase in the concentration of the specific material in the etchant. The etchant includes at least one, of the primary etchant, the first additive, and the second additive. The first additive and the second additive are separately supplied to the process bath.

Method of wet etching and method of fabricating semiconductor device using the same

The inventive concepts provide a method of completely removing a damage region of a surface of an etch target layer after plasma-etching the etch target layer. The method includes performing a first post-etch plasma treatment process using a first post-treatment gas on the plasma-etched etch target layer. A polarity of ions of the first post-treatment gas may be the same as a polarity of bias power applied to a stage in a plasma apparatus.

Method of treating a layer

A semiconductor memory device is disclosed. The device may include a stack including gate electrodes stacked on a substrate in a vertical direction and insulating patterns interposed between the gate electrodes, vertical channels passing through the stack and connected to the substrate, a tunnel insulating layer enclosing each of the vertical channels, charge storing patterns provided between the tunnel insulating layer and the gate electrodes and spaced apart from each other in the vertical direction, blocking insulating patterns provided between the charge storing patterns and the gate electrodes and spaced apart from each other in the vertical direction, and a bit line crossing the stack and connected to the vertical channels. The blocking insulating patterns may have a vertical thickness that is greater than that of the gate electrodes.

Three dimensional semiconductor memory devices and methods of fabricating the same are provided. According to the method, sacrificial layers and insulating layers are alternately and repeatedly stacked on a substrate, and a cutting region penetrating an uppermost sacrificial layer of the sacrificial layers is formed. The cutting region is filled with a non sacrificial layer. The insulating layers and the sacrificial layers are patterned to form a mold pattern. The mold pattern includes insulating patterns, sacrificial patterns, and the non sacrificial layer in the cutting region. The sacrificial patterns may be replaced with electrodes. The related semiconductor memory device is also provided.

Methods of fabricating three-dimensional semiconductor devices

A semiconductor device includes a polycrystalline semiconductor layer on a substrate, first and second stacks on the polycrystalline semiconductor layer, the first and second stacks extending in a first direction, a separation trench between the first and second stacks and extending in the first direction, the separation trench separating the first and second stacks in a second direction crossing the first direction, and vertical channel structures vertically passing through each of the first and second stacks, wherein the polycrystalline semiconductor layer includes a first grain region and a second grain region in contact with each other, the first and second grain region being adjacent to each other along the second direction, and wherein each of the first and second grain regions includes a plurality of crystal grains, each crystal grain having a longitudinal axis parallel to the second direction.

Semiconductor device and method of fabricating the same

A substrate having an insulating layer including an oxide is loaded into a chamber, and at least a part of the insulating layer is removed by injecting a process gas including an etching source gas into the chamber. The removal process is performed in a pulse type in which a first period and a second period are repeated a plurality of times. The etching source gas is supplied at a first flow rate during the first period and is supplied at a second flow rate less than the first flow rate during the second period. A temperature of the inside of the chamber remains at 100&#xb0; C. or more during the removal process.

Method of manufacturing semiconductor devices

Growing community of inventors

Seoul, South Korea

Kyunghyun Kim