Samsung Electronics Co., Ltd.

Kyungho Lee

Eunsub Shim

Masato Fujita

Junghyung Pyo

Jungbin Yun

Taesub Jung

Eun Sub Shim

Jung Bin Yun

Hyuk Soon Choi

Hyuk An

Hongsuk Lee

Doosik Seol

Bumsuk Kim

Kyungduck Lee

Taeyoung Oh

Kiheung Kim

Sungsoo Choi

Jongcheol Kim

Hwanwoong Kim

Seungjoon Lee

JungChak Ahn

Hyongryol Hwang

Sanghyuck Moon

Sung-Ho Choi

Sungjin Kim

Taehan Kim

Hyuncheol Kim

Seyoung Jang

Jihun Kim

Sangwon Ha

Sanghoon Park

Yunki Lee

Younoh Chi

Jungchul An

Jiwon Kim

Yun Ki Lee

Seungki Choi

Heegeun Jeong

Youngsun Lee

Wooseok Choi

Youngsun Oh

Wonchul Choi

Jongeun Park

Changhyun Park

Minchul Lee

Kwanghee Ryu

Sangjun Choi

Soyoung Jeong

Jeongjin Cho

Sung-ho Choi

Jueun Park

Kazunori Kakehi

Seungki Jung

Chulhyo Yoon

Dongyoung Jang

Seounghyun Kim

Seungki Baek

Minji Jung

Yunoh Chi

Heegeun Park

Jangho Moon

Heesang Kwon

Seoyun Park

An image sensor includes: (1) a substrate having first and second surfaces opposing each other in a first direction and a plurality of unit pixels, (2) first and second photodiodes disposed in the substrate in each of the plurality of unit pixels and isolated from each other in a second direction perpendicular to the first direction, (3) a first device isolation film disposed between the plurality of unit pixels, and (4) a pixel internal isolation film disposed in at least one of the plurality of unit pixels. A second device isolation film overlaps at least one of the first and second photodiodes in the first direction. A pair of third device isolation films: (a) extend from the first device isolation film into the unit pixel in a third direction perpendicular to the first direction and the second direction and (b) oppose each other.

Image sensor

A semiconductor memory device, including a memory cell array; a row hammer management circuit configured to: count a number of accesses based on an active command, and based on a first command applied after the active command, perform an internal read-update-write operation to read the count data from the count cells of a target memory cell row, and to write updated count data in the count cells of the target memory cell row; and a column decoder configured to: access a first memory cell using a first bit-line; and store data in the first memory cell using a first voltage, or perform an internal write operation to store the count data in the first memory cell using a second voltage greater than the first voltage during an internal write time interval smaller than a reference write time interval.

Semiconductor memory device and memory system including the same

An electronic device may include: a first housing; a second housing; a hinge structure; a display; and a sensor panel, wherein the sensor panel comprises: a support layer which comprises a polymer inclusive material and is in contact with an adhesive material arranged on at least one of a first surface of the first housing and a third surface of the second housing; a shielding layer arranged on the support layer; a first insulating layer arranged on the shielding layer; a first conductive pattern arranged on the first insulating layer; a second insulating layer arranged on the first conductive pattern; a second conductive pattern arranged on the second insulating layer; and a third insulating layer arranged on the second conductive pattern and facing one surface of the display, wherein the thickness of at least one of the first insulating layer and the third insulating layer is greater than the thickness of the second insulating layer.

Electronic device comprising sensor panel

Provided is an image sensor including a semiconductor substrate having first and second surfaces disposed opposite to the first surface, a pixel separation structure disposed in the semiconductor substrate and defining and surrounding a pixel region, first and second photoelectric conversion regions disposed in the semiconductor substrate on the pixel region, a first transfer gate electrode disposed on the first surface of the semiconductor substrate and between the first photoelectric conversion region and a first floating diffusion region, a second transfer gate electrode disposed on the first surface of the semiconductor substrate and between the second photoelectric conversion region and a second floating diffusion region, a pixel gate electrode disposed on the first surface of the semiconductor substrate and overlapping one of the first and second photoelectric conversion regions, and impurity regions disposed on opposite sides of the pixel gate electrode.

Image sensor with pixel separation structure

An image sensor includes a pixel array and a logic circuit. The pixel array includes a pixel isolation layer between a plurality of pixels. Each of the plurality of pixels include a pixel circuit below at least one photodiode. The logic circuit acquires a pixel signal from the plurality of pixels. The pixel array includes at least one autofocusing pixel, which includes a first photodiode, a second photodiode, a pixel internal isolation layer between the first and second photodiodes, and a microlens on the first and second photodiodes. The pixel internal isolation layer includes a first pixel internal isolation layer and a second pixel internal isolation layer, separated from each other in a first direction, perpendicular to the upper surface of the substrate, and the first pixel internal isolation layer and the second pixel internal isolation layer include different materials.

An image sensor and an operating method of the image sensor may include a pixel array including a plurality of pixels; a controller configured to generate a pre-shutter driving signal associated with a pre-shutter operation, the pre-shutter driving signal generated before a first shutter operation and a first read operation corresponding to photographing a first frame is performed; a row driver configured to drive first control signals to the pixel array based on the pre-shutter driving signal, the first control signals associated with the pre-shutter operation; and the pixel array is configured to perform the pre-shutter operation in response to the first control signals, wherein levels of the first control signals correspond to levels of second control signals, the second control signals associated with the first read operation.

Image sensor and operating method thereof

A method of operating an image sensor includes accumulating first charges through a photo diode, applying a first transfer gate signal having a first voltage level to a transfer transistor, performing, through a reset transistor, a first reset operation on a floating diffusion node connected with the reset transistor and the transfer transistor, changing the first voltage level of the first transfer gate signal to a second voltage level higher than the first voltage level, during the first reset operation, changing the second voltage level of the first transfer gate signal to a third voltage level higher than the second voltage level, and changing the third voltage level of the first transfer gate signal to the second voltage level.

Image sensor using transfer gate signal having three voltage levels, and method of operating the same

An image sensor includes a two-dimensional array of image sensor pixels, which are formed in a semiconductor layer. Each image sensor pixel is formed in a substrate having a corresponding semiconductor region therein. Each semiconductor region contains at least first and second photoelectric conversion elements, which are disposed at side-by-side locations therein. An electrically insulating isolation region is also provided, which extends at least partially through the semiconductor region and at least partially between the first and second photoelectric conversion elements, which may be configured respectively as first and second semiconductor regions of first conductivity type (e.g., N-type). At least one optically reflective region is also provided, which extends at least partially through the semiconductor region and surrounds at least a portion of at least one of the first and second photoelectric conversion elements. A semiconductor floating diffusion (FD) region (e.g., N-type region) is provided within the semiconductor region.

Image sensors with light channeling reflective layers therein

An image sensor includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a transfer gate electrode provided on the first surface of the semiconductor substrate, readout circuit transistors spaced apart from the transfer gate electrode and provided on the first surface of the semiconductor substrate, and a photoelectric conversion layer provided in the semiconductor substrate at a side of the transfer gate electrode and including dopants of a first conductivity type. The photoelectric conversion layer includes a first region having a first thickness and a second region having a second thickness that is less than the first thickness. The second region overlaps with at least a portion of the readout circuit transistors in a direction perpendicular to the first surface of the semiconductor substrate.

An image sensor is provided. The image sensor includes: a pixel array including first and second pixel groups, each of which includes unit pixels arranged in 4×4 array, each of the unit pixels including a photodiode provided, and the first and second pixel groups being alternately disposed in multiple directions; a logic circuit configured to acquire pixel signals from the unit pixels; first microlenses provided on corresponding unit pixels in the first pixel groups; and second microlenses provided on four corresponding unit pixels of the unit pixels included in the second pixel groups. Each of the first and second pixel groups includes a device isolation layer provided between the unit pixels, and a color filter provided on the first surface, and each of the second pixel groups includes an overflow region configured to move electrical charges between adjacent photodiodes.

Image sensor comprising a pixel array including first pixel groups and second pixel groups with corresponding microlenses of different sizes for autofocusing

An image sensor according to the present disclosure includes: a first pixel group, which includes a first pixel unit corresponding to a first color, and a plurality of first pixels arranged with an m×n form. The image sensor further includes a second pixel unit, which corresponds to a second color, and a plurality of second pixels arranged with the m×n form. The image sensor further includes a third pixel unit, which corresponds to a third color, and a plurality of third pixels arranged with the m×n form, and m and n are natural numbers greater than or equal to 3. A first micro lens is formed on the first pixel unit and shared by at least two adjacent first pixels in a first direction among the plurality of first pixels.

Image sensor including phase detection pixels

A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit and a control logic circuit. The row hammer management circuit stores counted values in count cells of each of the plurality of memory cell rows as count data based on an active command applied to the control logic circuit at a first time point, and performs an internal read-update-write operation to read the count data from the count cells of a target memory cell row from among the plurality of memory cell rows, to update the count data that was read to obtain updated count data, and to write the updated count data in the count cells of the target memory cell row in response to a precharge command applied at a second time point after a first command that is applied to the control logic circuit.

An image sensor includes a first photodiode group, a second photodiode group, a first transfer transistor group, a second transfer transistor group, a floating diffusion region of a substrate in which electric charges generated in the first photodiode group are stored, and a power supply node for applying a power supply voltage to the second photodiode group. A barrier voltage is applied to at least one transfer transistor of the second transfer transistor group. The power supply voltage allows electric charges, generated in the second photodiode group, to migrate to the power supply node, and the barrier voltage forms a potential barrier between the second photodiode group and the floating diffusion region.

An image sensor includes a pixel array including pixels, wherein each pixel includes at least one photodiode generating electrical charge and a pixel circuit providing a pixel signal based on the electrical charge. The images sensor also includes a logic circuit configured to generate an image based on the pixel signal, wherein the pixel circuit includes a parallel-connected first reset transistor and second reset transistor, and the logic circuit determines whether the second reset transistor is turned ON/OFF based on a level of incident light received by the at least one photodiode during an exposure time period.

A semiconductor memory device includes a memory cell array including a plurality of memory cell rows and a row hammer management circuit. The row hammer management circuit stores counted values in count cells of each of the plurality of memory cell rows as count data, and performs an internal read-update-write operation to read the count data from the count cells of a target memory cell row from among the plurality of memory cell rows, to update the count data that was read to obtain updated count data, and to write the updated count data in the count cells of the target memory cell row. The row hammer management circuit includes a hammer address queue. The row hammer management circuit changes the updated count data randomly, based on an event signal indicating a state change of the hammer address queue.

Growing community of inventors

Suwon-si, South Korea

Kyungho Lee