Lg Electronics Inc.

Samsung Display Co., Ltd.

I-sens, Inc.

Daegu Gyeongbuk Institute of Science and Technology

Konkuk University Industrial Cooperation Corp

Bitnine Co., Ltd.

Kyungho Kim

Jinpil Kim

Kyoungsoo Moon

Hyeonjae Lee

Seungjoo An

Joonhui Lee

Sejin Oh

Aettie Ji

Sanghyun Kim

Gomer Thomas

Jinwon Lee

Jaehee Chung

Jongyeul Suh

Hotaek Hong

Kwansuk Kim

Gichang Lee

Kangsuk Huh

Byungsun Park

Dongwan Seo

Sungok Park

Youngjae Seo

Seungryul Yang

Waqar Zia

Minsoo Lee

Younghwan Kwon

Donghee Shin

Janghun Bae

Byeongmoon Jeon

Sangoh Jeong

Jangwoong Park

Sang Yong No

Nahyeon Cha

Sangyong No

Jaekoo Lee

Hendry Hendry

Jungsun Kim

Yonghee Lee

Seok-Won Lee

Dong-Yoon Lee

Daesuk Kim

Donghyeon Ki

Jae Phil Do

Ok-kyung Park

Jeongyoon Lee

Yungjoon Jin

Yusung Kim

Seong-Min Kim

Jinkwon Lim

Gunhee Kim

Donghyun Kang

Chaungi Choi

Kisung Kim

Jinkoo Chung

Seongyoung Lee

Byoungsun Na

Sunkwun Son

Sangchul Park

Sungchun Cho

Keechan Park

Hyukjin Kim

Kiwon Park

Jongsun Kang

Eunkyoung Nam

Euiseok Shin

Jaewon Jung

Juhyeon Bae

Nokyung Park

Yikyoung You

Sejiin Oh

Kawansuk Kim

Waqar Jia

Jooho Shin

Hyeonju Jeong

Areum Jo

Choelsun Kang

Hyeongjae Lee

Kwanmo Kim

Jung Uk Ha

Sang Taek Shin

A pixel includes a first transistor coupled to a first node, a second transistor receiving a writing signal, a third transistor receiving a compensation signal, a first terminal coupled to the third node, and a second terminal coupled to a fourth node, a fourth transistor receiving an initialization signal, a first terminal coupled to the fourth node, and a second terminal coupled to an initialization voltage line, a fifth transistor receiving a first emission signal, a first terminal coupled to the first power supply voltage line, and a second terminal coupled to the second node, a light emitting element coupled to the third node and a second power supply voltage line, and an eighth transistor receiving a second emission signal, a first terminal coupled to the first node, and a second terminal coupled to the fourth node.

Pixel of a display device and display device

A gate driver includes first to nstages. A kstage among the first to nstages includes a first transistor including a second terminal electrically connected to a first control node, a fifth transistor including a gate electrically connected to an inverting control node, a sixth transistor including a gate electrically connected to a second control node, a fourth transistor including a gate which receives a low gate voltage, a first terminal electrically connected to a first control node, a second terminal electrically connected to a second control node, and a back gate, and a seventh transistor including a gate which receives a voltage of the inverting control node of a k+1stage, a first terminal which receives a voltage of the first control node or the second control node of a k−1stage, and a second terminal electrically connected to the back gate of the fourth transistor.

Gate driver and display device including the same

A stage of a gate driving circuit includes a first control circuit connected to a first voltage input terminal receiving a first voltage and a second voltage input terminal receiving a second voltage lower than the first voltage, the first control circuit being configured to control voltage levels of a first control node and a second control node; a first output circuit connected to a first clock terminal and a third voltage input terminal receiving a third voltage, the first output circuit being configured to output a gate signal according to the voltage levels of the first control node and the second control node; and a second output circuit connected to a second clock terminal and the second voltage input terminal, the second output circuit being configured to output a carry signal according to the voltage levels of the first control node and the second control node.

Gate driving circuit

A driving circuit includes stages, each of the stages including: a first control circuit connected to a first voltage input terminal and a second voltage input terminal, and to control voltage levels of a first control node, a second control node, and a third control node; a first output circuit connected to a first clock terminal and a third voltage input terminal, and to output a first output signal according to the voltage levels of the first control node and the second control node; a second output circuit connected to a second clock terminal and the second voltage input terminal, and to output a second output signal according to the voltage levels of the third control node and the second control node; and a boosting circuit connected to a third clock terminal and the second voltage input terminal, and to boost the voltage level of the first control node.

Driving circuit

A display panel includes a transistor, a light emitting element, a pixel defining layer, a separator, and a sensing electrode. The light emitting elements includes a first electrode, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer. The second electrode is electrically connected to the transistor. The pixel defining film is disposed on the first electrode and defines an emission opening above the first electrode. The separator is disposed on the pixel defining film. The sensing electrode is disposed on the separator. The sensing electrode and the second electrode are electrically separated by the separator.

Display panel including sensing electrode and electrode of light emitting element electrically separated by at least one separator and display device including the same

A gate driving circuit includes: a first pull up control circuit for controlling a voltage of a pull up control node in response to a previous carry signal; a pull down control circuit for controlling a voltage of a pull down control node in response to the voltage of the pull up control node; a boosting circuit including a boosting capacitor and for boosting the voltage of the pull up control node; a gate output circuit for outputting a plurality of gate signals having different timings in response to the voltage of the pull up control node and the voltage of the pull down control node; and a stabilizing circuit including a control electrode connected to an end of the boosting capacitor, a first electrode for receiving a first high power voltage and a second electrode connected to the first pull up control circuit.

Gate driving circuit and display apparatus including the same

A gate signal masking circuit includes a first switching element including a control electrode connected to a masking node, a first electrode connected to a first node and a second electrode connected to a third node, a second switching element including a control electrode receiving a carry signal, a first electrode receiving a masking signal and a second electrode connected to a fourth node, a third switching element including a control electrode receiving a first enable signal, a first electrode connected to the fourth node and a second electrode connected to the masking node, a fourth switching element including a control electrode receiving a second enable signal, a first electrode connected to the masking node and a second electrode connected to a fifth node and a fifth switching element including a control electrode receiving the carry signal, a first electrode connected to the fifth node and a second electrode.

Gate signal masking circuit, gate driver including the same and display apparatus including the same

A display device includes a display layer that displays an image, and a sensing layer that is disposed on the display layer and includes a plurality of first sensing electrodes and a plurality of second sensing electrodes intersecting the plurality of first sensing electrodes. The display layer may include a transistor, a light emitting device, which includes a first electrode, an intermediate electrode disposed on the first electrode, and a second electrode disposed on the intermediate electrode, a pixel defining film, in which an emission opening portion overlapping a portion of the first electrode is defined, and a separator which is disposed on the pixel defining film and interrupting a continued formation of the second electrode. The plurality of first sensing electrodes and the plurality of second sensing electrodes may overlap the separator.

Display device

A display panel includes a first display region to an N-th display region disposed in a row direction. A P-th display region includes a first pixel circuit including a first pixel driving transistor, a first pixel initialization transistor which receives an initialization voltage, and a first pixel compensation transistor connected in series to the first pixel initialization transistor, where the first pixel compensation transistor connects the first pixel driving transistor and the first pixel initialization transistor to each other based on a compensation gate signal, and a P-th region control circuit including a first control transistor which outputs a high gate voltage of the compensation gate signal, and a second control transistor which outputs a low gate voltage of the compensation gate signal, where the first control transistor and the second control transistor are controlled based on a P-th region control signal.

Display panel and display device including the same

A scan driver includes: stages. Each stage includes: a first node control circuit for controlling a voltage of a first node; an inverted carry node control circuit for controlling a voltage of an inverted carry node; a carry output circuit for outputting a carry signal; a fourth node control circuit for controlling a voltage of a fourth node in response to the carry signal; a second node control circuit for controlling a voltage of a second node in response to the carry signal, an enable signal, and the voltage of the inverted carry node; a third node control circuit for controlling a voltage of a third node in response to the voltage of the second node and the voltage of the fourth node; and a scan output circuit for outputting a scan signal in response to the voltage of the third node and the voltage of the fourth node.

Scan driver having a node control circuit in response to carry signal, enable signal, and voltage of inverted carry node and display device including the same

A gate driver including a plurality of stages. Each of the plurality of stages includes a first masking controlling circuit including a control circuit, a carry output circuit, a first enable node controlling circuit, a first masking circuit, a first gate output circuit, and a second masking controlling circuit including a second enable node controlling circuit, a second masking circuit and a second gate output circuit. The first masking controlling circuit and the second masking controlling circuit shares the control circuit and the carry output circuit.

A gate driving circuit includes a capacitor connected between a first gate of a pull-down transistor and a control node, and a control transistor connected between the control node and a ground terminal and having a gate connected to the ground terminal.

Transmission gate circuit, inverter circuit and gate driving circuit including the same

A cartridge capable of a centrifugation and an automatic analysis according to an embodiment of the present invention includes: at least two or more sample wells, a centrifugation well, a measuring well, and a tip receiving well, in which a container is formed into a lower portion along a circumference of a circular plate with a predetermined interval, wherein the centrifugation well is sealed with one lid paper along with at least two or more of the sample wells, a blood injection unit is further formed inside of a radius direction for the centrifugation well, the blood injection unit has an outer blood injection hole formed to be spaced inside the centrifugation well in the radius direction, an inclined passage that communicates with the centrifugation well from the outer blood injection hole, and a cover integrally attached to the outer blood injection hole to open and close the blood injection hole.

Cartridge capable of centrifugal separation and automatic analysis

A scan driver includes a plurality of stages. Each of the plurality of stages includes a control circuit which controls a voltage of a first node and a voltage of a second node in response to an input signal, a first clock signal and a second clock signal, a carry output circuit which outputs a carry signal in response to the voltage of the first node and the voltage of the second node, an enable node controlling circuit which controls a voltage of an enable node in response to the carry signal, an enable signal and an inverted enable signal, a masking circuit which controls a voltage of a third node in response to the voltage of the second node and the voltage of the enable node, and a scan output circuit which outputs a scan signal in response to the voltage of the first node and the voltage of the third node.

Scan driver and display device

A display panel includes gate lines, data lines, switching elements connected to the gate lines and the data lines, pixel electrodes connected to the switching elements and markers. The pixel electrode includes first, second third and fourth areas which are divided by a horizontal central line and a vertical central line. The first, second, third and fourth areas correspond to an upper-left portion, an upper-right portion, a lower-left portion and a lower-right portion of a central point of the pixel electrode. When the pixel electrode is disposed between first and second data lines and connected to the first data line, the marker is disposed in one of the first and third areas. When the pixel electrode is disposed between the first and second data lines and connected to the second data line, the marker is disposed in one of the second and fourth areas.

Display panel and method of repairing the same

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Seoul, South Korea

Kyungho Kim