Samsung Electronics Co., Ltd.

Kyung-wook Lee

Nae-in Lee

Geum-jong Bae

Hwa-sung Rhee

Tae-hee Choe

Sang-su Kim

Gi-ho Cha

Chi-jung Kang

Byoung-hun Lee

Byung-hun Lee

CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A SiGelayer is also disposed between the electrically insulating layer and the unstrained silicon active layer. The SiGelayer forms a first junction with the unstrained silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface of the unstrained silicon active layer. The peak Ge concentration level is greater than x=0.15 and the concentration of Ge in the SiGelayer varies from the peak level to a level less than about x=0.1 at the first junction. The concentration of Ge at the first junction may be abrupt. More preferably, the concentration of Ge in the SiGelayer varies from the peak level where 0.2&#x3c;x&#x3c;0.4 to a level where x=0 at the first junction. The SiGelayer also has a retrograded arsenic doping profile therein relative to the surface. This retrograded profile may result in the SiGelayer having a greater concentration of first conductivity type dopants therein relative to the concentration of first conductivity type dopants in a channel region within the unstrained silicon active layer. The total amount of dopants in the channel region and underlying SiGelayer can also be carefully controlled to achieve a desired threshold voltage.

CMOS integrated circuit devices and substrates having buried silicon germanium layers therein and method of forming same

Methods of forming CMOS integrated circuit devices and substrates having buried silicon germanium layers therein

CMOS integrated circuit devices and substrates having buried silicon germanium layers therein and methods of forming same

CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si Ge layer is also disposed between the electrically insulating layer and the unstrained silicon active layer. The Si Ge layer forms a first junction with the unstrained silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface of the unstrained silicon active layer. The peal Ge concentration level is greater than x&equals;0.15 and the concentration of Ge in the Si Ge layer varies from the peak level to a level less than about x&equals;0.1 at the first junction. The concentration of Ge at the first junction may be abrupt. More preferably, the concentration of Ge in the Si Ge layer varies from the peak level where 0.2<x<0.4 to a level where x&equals;0 at the first junction. The Si Ge layer also has a retrograded arsenic doping profile therein relative to the surface.

CMOS integrated circuit devices and substrates having unstrained silicon active layers

An apparatus for bonding semiconductor wafers firmly bonds the wafers to each other and can always lay the bonded wafers on a desired bonding plate. The bonding plates have a plurality of grooves formed on their respective surfaces to reduce the bond force between the wafers and the bonding plates of the apparatus, and to prevent the wafers from sliding off the plates due to an air cushion. An interval controlling pin projects from the surface of one of the bonding plates to reduce breakage of the wafers by maintaining an interval between the bonding plates as they are are rotated towards each other. An elastic pad portion is installed on one the bonding plates for providing an elastic force for the wafers placed on the bonding plates so that the wafers bond to each other properly when the bonding plates are further rotated towards each other.

Apparatus for bonding semiconductor wafers

A SOI substrate manufacturing method which corrects the warpage in the SOI substrate by varying the thickness of a semiconductor material layer additionally formed over the bonded combination of a semiconductor substrate and supporting substrate.

SOI substrate manufacturing method

Growing community of inventors

Kyungki-do, South Korea

Kyung-wook Lee