Samsung Electronics Co., Ltd.

Kyung-Woo Nam

Yong-Jun Kim

Chi-Sung Oh

Hyun-Suk Lee

Ho-Cheol Lee

Soo-Young Kim

Jin-Kuk Kim

Dong-Hyuk Lee

Han-gu Sohn

Ho-cheol Lee

Jong-Wook Park

Jin-hyoung Kwon

You-Mi Lee

Kwang-Myeong Jang

Song-Won Kim

A multi-port memory device includes a refresh register and a refresh controller for preventing refresh starvation in a shared memory unit of the memory device. The memory device further includes a plurality of ports sharing access to the shared memory unit. The refresh register stores information regarding at least one refresh command. The refresh controller determines whether to activate an internal refresh operation at a transition in port authority according to such information stored in the refresh register.

Method, device, and system for preventing refresh starvation in shared memory bank

A multiport semiconductor memory device includes; first and second port units respectively coupled to first and second processors, first and second dedicated memory area accessed by first and second processors, respectively and implemented using DRAM cells, a shared memory area commonly accessed by the first and second processors via respective first and second port units and implemented using memory cells different from the DRAM cells implementing the first and second dedicated memory areas, and a port connection control unit controlling data path configuration between the shared memory area and the first and second port units to enable data communication between the first and second processors through the shared memory area.

Multi port memory device with shared memory area using latch type memory cells and driving method

A multipath accessible semiconductor memory device having a mailbox area and a mailbox access control method thereof are provided. The semiconductor memory device includes N number of ports, at least one shared memory area allocated in a memory cell array, and N number of mailbox areas for message communication. The at least one shared memory area is operationally connected to the N number of ports, and is accessible through a plurality of data input/output lines to form a data access path between the at least one shared memory area and one port, having an access right to the at least one memory area, among the N number of ports. The N number of mailbox areas are provided in one-to-one correspondence with the N number of ports and are accessible through the plurality of data input/output lines when an address of a predetermined area of the at least one shared memory area is applied to the semiconductor memory device. An efficient layout of mailboxes and an efficient message access path can be obtained.

Multi-path accessible semiconductor memory device having mailbox areas and mailbox access control method thereof

A semiconductor memory device and a self-refresh method in which the semiconductor memory device includes a plurality of input/output ports having respective independent operation, a period of self-refresh through one of the plurality of input/output ports being subordinate to a kind of operation through another input/output port. Whereby, a refresh characteristic in a multi-port semiconductor memory device including a dual-port semiconductor memory device may be improved.

Semiconductor memory device and self-refresh method therefor

A multi-memory chip and data transfer method are capable of directly transferring data between internal memory devices. The multi-memory chip of the present invention includes a first memory device, a second memory device, and a data transmission bus that is shared by the memory devices. Furthermore, the second memory device includes a mode register set for setting an internal transfer mode. In accordance with the data transfer method according to the present invention, the transfer of data between the memory devices included in the multi-memory chip is performed through the data transmission bus shared by the memory devices. Accordingly, the multi-memory chip and the data transfer method can considerably improve data transfer rates between devices, as compared to conventional approaches in which data is transferred to the DMA controller of an external system.

Multi-memory chip and data transfer method capable of directly transferring data between internal memory devices

A semiconductor memory device comprises a plurality of memory cells connected to a plurality of word lines grouped in word line sets. Each of the word line sets is connected to a word line enable signal generation unit which stores information indicating whether data has been written to any of the memory cells connected to the word line set. The word line enable signal generation unit controls refresh operations for memory cells connected to the word line set so that only word lines connected to memory cells that have been programmed are refreshed.

Semiconductor memory device capable of selectively refreshing word lines

A semiconductor memory device includes a column enable signal generator, a row enable signal generator and a final column enable signal generator. The column signal enable generator may generate a latency control signal and generating a buffered clock signal as a column enable signal in response to the latency control signal. The row enable signal generator may generate a row enable signal. The final column enable signal generator may generate a first signal in response to the column enable signal, a second signal in response to the row enable signal, and may output the first and/or the second signal as a final column enable signal.

Semiconductor memory devices and methods for generating column enable signals thereof

A semiconductor memory device is operable in a full capacity mode and at least one reduced capacity mode, and includes a memory array having a plurality of memory blocks, each of the memory blocks having at least one word line. An address generation circuit generates a first multi-bit address signal having a logic value which is sequentially incremented by one during each of successive refresh periods. An address sorting circuit receives the first multi-bit address signal and outputs a second multi-bit address signal in which one or more least significant bits of the first multi-bit address signal are arranged in the second multi-bit address signal to indicate a memory block of the memory array, and in which remaining bits of the first multi-bit address signal are arranged in the second multi-bit address to indicate a word line within the selected memory block. The word lines of the memory array are refreshed according to the second multi-bit address signal.

Semiconductor memory having variable memory size and method for refreshing the same

A word line enable timing determination circuit of a memory device and method of determining word line enable timing in a memory device may be configured to adjust enable timing at which to activate a word line for at least one read/write command input to the memory device. This may be based on whether the memory device is performing a hidden refresh operation. In an example, and when a read/write command is input to the memory device, a word line for the read/write command may be activated after a first delay if the memory device is not executing a hidden refresh operation. Otherwise, a word line for the read/write command is activated after a second delay.

Word line enable timing determination circuit of a memory device and methods of determining word line enable timing in the memory device

In the refresh type semiconductor memory device having a plurality of refresh type memory cells, for internally performing a refresh operation without an external command together with an input and output operation of data; the refresh type semiconductor memory device includes a refresh circuit having a compulsive refresh request signal generator that disables a refresh request cut-off signal, in response to a signal responding to an active transition of a write enable signal, and a dummy refresh signal generated in a read operation, so as to prevent a refresh fail causable in a consecutive write operation, whereby improving a write cycle time and minimizing a refresh fail at a high speed operation.

Refresh type semiconductor memory device having refresh circuit for minimizing refresh fail at high speed operation

A refresh operation in a PSRAM device to hidden-refresh an internal memory cell by using a refresh pulse signal may be controlled by forming a dummy duration for the refresh operation in a read/write cycle, reducing the dummy duration when the refresh pulse signal is not generated, and delaying the read/write cycle until the refresh operation is completed, when the refresh pulse signal is generated. The dummy duration may be reduced by a given amount during a period in which the refresh operation is not being performed, while the dummy duration may be increased in period of time subject to the refresh operation.

Refresh control circuit and methods of operation and control of the refresh control circuit

A refresh control circuit is provided for controlling refresh cycles according to values stored in a register. A related refreshing method is also provided. The refresh control circuit controls the refresh cycles so as to refresh data stored in memory cells. The refresh control circuit includes a refresh counter for generating a plurality of frequency division signals by dividing a clock signal in response to a refresh signal for directing a refresh operation. The refresh control circuit also includes a refresh activation signal generator for generating a refresh activation signal corresponding to the refresh cycle according to values stored in a register.

Refresh control circuit for controlling refresh cycles according to values stored in a register and related refreshing method

Graphics memory devices include an output register having an input electrically coupled to an output signal line (DO) and first and second data output buffers responsive to first and second clock signals (CLK1, CLK2), respectively. The first data output buffer has an input electrically coupled to the output signal line (DO) and the second data output buffer has an input electrically coupled to an output of the output register. These memory devices also include at least one memory cell array and a read data driver that has an input electrically coupled to the memory cell array by an input/output signal line (I/O) and an output electrically coupled to the output signal line (DO). To provide improved performance for graphics processing applications, a clock signal generator is provided that generates the first and second clock signals at different frequencies and/or different phases relative to each other. The second clock signal is preferably generated at a higher frequency than the first clock signal so that data (e.g., screen refresh data) provided by the read data driver to the output register can be serially transmitted from the second data output buffer at a high data rate. This data can also be transmitted in parallel with data being transmitted from the first data output buffer. In particular, the first data output buffer generates data at its output (first port) in response to a rising or falling edge of the first clock signal, but the second data output buffer generates data at its output (second port) in response to rising and falling edges of the second clock signal. Thus, even if the first and second clock signals have the same frequency, the rate of data being transmitted by the second data output buffer can be higher than the rate of data being transmitted by the first data output buffer.

Growing community of inventors

Seoul, South Korea

Kyung-Woo Nam