Arm Limited

Kyung Woo Kim

Hsin-Yu Chen

Andy Wangkun Chen

Edward Martin McCombs, Jr

Rahul Mathur

Mohit Chanana

Shruti Aggarwal

Phani Raja Bhushan Chalasani

Various implementations described herein are directed to a device having memory circuitry with bitlines coupled to an array of bitcells. The device may include precharge circuitry that precharges the bitlines during modes of operation including a standby mode of operation and an active mode of operation. In some instances, the precharge circuitry may include a low power mode of operation that prevents precharge of the bitlines during the standby mode of operation.

Precharge circuitry for use with bitlines

According to one implementation of the present disclosure, a method includes determining one or more of a read current threshold, a leakage current threshold or a minimum assist voltage threshold; identifying a logic design, wherein the logic design is based the on one or more of the read current threshold, the leakage current threshold, or the minimum assist voltage threshold; identifying a bitcell-type and a corresponding version of the bitcell-type, wherein each version of the bitcell-type is associated with performance and power attributes of a bitcell of a memory array; and determining a memory optimization mode based on the identified logic design and the identified version of the bitcell-type.

Methods and apparatuses of configurable integrated circuits

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Austin, TX, United States of America

Kyung Woo Kim