Skhynix Inc.

Hynix Semiconductor Inc.

Kyung Whan Kim

Dong Uk Lee

Dae Suk Kim

Sung Joo Ha

Sun Hwa Park

Kee Yun Kim

Ah Reum Han

Dong Kyun Kim

Jin Ho Jeong

Mun Seon Jang

Hak Song Kim

Sung Chun Jang

Sungchun Jang

A semiconductor module includes an address control circuit configured to generate an internal address based on an address in a first read operation and a second read operation that are sequentially performed and configured to generate multiple decoding enable signals and an error information enable signal, a memory circuit including multiple mats and configured to output internal data based on the internal address and the multiple decoding enable signals in the first read operation and configured to output internal meta data and second internal parities based on the internal address and the multiple decoding enable signals in the second read operation, and an error information storage circuit configured to output first internal parities based on the internal address and the error information enable signal in the first read operation.

Semiconductor module for performing error correction operation

A method for operating a memory includes determining to perform an error correction operation; determining whether to perform an error correction operation; generating an internal address when the error correction operation is performed; reading data from memory cells that are selected based on the internal address and an error correction code corresponding to the data; performing an error correction operation on the data based on the error correction code to produce an error-corrected data; writing the error-corrected data and an error correction code corresponding to the error-corrected data into the memory cells; determining one or more regions among regions in the memory as a repair-requiring region based on an error detected when the error correction operation is performed; receiving a first command; backing up the data and the error correction code into a redundant region in response to the first command; and repairing the repair-requiring region with the redundant region.

Memory, memory system, operation method of the memory, and operation of the memory system

A memory system may include a controller; and a plurality of memory modules, wherein a data input and output of the plurality of memory modules is performed with a single channel manner according to an address signal provided from the controller in common, wherein each of the plurality of memory modules includes a buffer chip and a plurality of memory chips coupled to the buffer chip, wherein all the buffer chips of the plurality of memory modules are directly coupled to the controller through independent input and output bus.

Memory module and memory system including the memory module

A semiconductor device includes a delay-locked clock generation circuit configured to generate a delay-locked clock which is driven by at least one internal clock selected from a plurality of internal clocks in response to a phase control signal. The semiconductor device also includes a latency command generation circuit configured to generate a latency command for generating transmission data from data by latching an internal command sequentially by the at least one internal clock in response to the phase control signal and shifting the sequentially latched internal command by a period set by a shifting control signal in response to the delay-locked clock.

Semiconductor device

An internal clock generation circuit includes an interpolation clock generation circuit and a locked clock generation circuit. The interpolation clock generation circuit generates an interpolation clock signal from a division clock signal in response to a switching control signal and a current control signal. The locked clock generation circuit includes an oscillator and generates a locked clock signal for generating an internal clock signal from the interpolation clock signal.

Internal clock generation circuits

A semiconductor device includes a first mode signal generation circuit suitable for generating a first mode signal in response to a command, the first mode signal being enabled in the case where a first period determined depending on a current characteristic of a first MOS transistor is longer than a second period determined by a first passive element; and a second mode signal generation circuit suitable for generating a second mode signal in response to the command, the second mode signal being enabled in the case where a third period determined by a second passive element is longer than a fourth period determined depending on a current characteristic of a second MOS transistor.

Semiconductor device for generating mode signals including information on the current characteristics

A semiconductor apparatus includes a plurality of dies. Any one of the dies may be set to a first rank and another of the dies may be set to a second rank. One or more of the first and second ranks may be configured to output any one of an even-numbered byte and an odd-numbered byte through an input/output stage at a timing earlier than the other one, according to a read command.

Semiconductor apparatus having multiple ranks with noise elimination

A semiconductor device may be provided. The semiconductor device may include an input information signal generation circuit and a command generation circuit. The input information signal generation circuit may be configured to latch a command in synchronization with a point of time that a division clock signal is inputted. The command generation circuit may be configured to shift a phase of the latched command in synchronization with a multiplication clock signal to shift the command.

Semiconductor devices

A stack package may include a first chip, a second chip, a through silicon via (TSV) and an interface circuit unit. The first chip may include a first internal circuit unit driven by an internal voltage. The second chip may be stacked over the first chip. The second chip may include a second internal circuit unit driven by the internal voltage. The TSV may be electrically coupled between the first chip and the second chip. The interface circuit unit may be arranged in the first chip and the second chip. The interface circuit unit may be coupled to the TSV. A portion of the interface circuit unit may be received a variable voltage different from the internal voltage as a driving voltage.

Stack package and semiconductor integrated circuit device including a variable voltage

A plurality of memory blocks; and a control block configured to independently operate a part of the plurality of memory banks as a first sub-channel and a remainder of the plurality of memory banks as a second sub-channel according to whether a sub-channel is set.

Semiconductor integrated circuit

An oscillator operates with a variable driving voltage to produce an oscillation signal of a predetermined period in a semiconductor device. The oscillator has a plurality of logic devices connected to each other in a form of a ring. The oscillator includes a voltage generating circuit for generating first and second driving voltages which are selectively applied to the logic devices. The selective application of the first or second driving voltage to the logic devices affects the period of the oscillation signal produced. The first driving voltage is applied to the logic devices for normal operations when the oscillation signal period is tested to substantially equal the predetermined period. The second driving voltage is applied to the logic devices for normal operations when the oscillation signal period is tested to be different from the predetermined period. The second driving voltage is adjusted by changing the resistance ratio of at least two resistors in the circuit.

Oscillator circuit operating with a variable driving voltage

A multi-loop oscillator which can control variation of an oscillating frequency of a ring oscillator according to variation of a supply voltage is disclosed comprising: first to Nth delay loops, wherein oscillation signal having a predetermined period is generated by selecting one of first to Nth delay loops according to potential variation of a supply voltage. Herein, the multi-loop oscillator further comprises a loop selection section for selecting one loop from among the first to the Nth delay loops, according to potential variation of the supply voltage. Further, the multi-loop oscillator further comprises a supply voltage detection circuit section for detecting variation of the supply voltage, and the supply voltage detection circuit section controls an operation of the loop selection section. In the multi-loop oscillator, an oscillation frequency of the ring oscillator can be adjusted. Accordingly, when the ring oscillator is employed, an abnormal operation of a pumping circuit operating in response to an oscillation signal of the ring oscillator can be considerably reduced.

Multi-loop oscillator

A power-up circuit comprises a first PMOS transistor connected between the power supply and a first node, wherein a gate terminal of the first PMOS transistor is connected to the ground, a first voltage divider for dividing the power upon a power up, a first NMOS transistor driven an output of the first voltage divider upon a power up and connected between the first node and the ground, an inverter having a plurality of PMOS transistors connected between the power supply and a second node, in which gate electrodes of the plurality of inverter are connected from each other and a second NMOS transistor connected between the second node and the ground and gate of the second NMOS transistor is connected to the plurality of the PMOS transistors, thereby inverting the potential of the first node, and a third NMOS transistor connected between the first node and the ground, wherein the third NMOS transistor is turned on by an output of the inverter, thereby preventing shifting faster than the potential of the first node.

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Seoul, South Korea

Kyung Whan Kim