Samsung Electronics Co., Ltd.

Kyung-tae Lee

Mu-kyeng Jung

Byung-jun Oh

Seong-ho Liu

Mu-Kyoung Jung

Integrated circuit devices include an integrated circuit substrate and a conductive lower electrode layer of a capacitor on the integrated circuit substrate. A dielectric layer is on the lower electrode layer and a conductive upper electrode layer of the capacitor is on the dielectric layer. A first intermetal dielectric layer is on the upper electrode layer. The first intermetal dielectric layer includes at least one via hole extending to the upper electrode layer. A first conductive interconnection layer is on the at least one via hole of the first intermetal dielectric layer. A second intermetal dielectric layer is on the first intermetal dielectric layer. The second intermetal dielectric layer includes at least one via hole extending to the first conductive interconnection layer and at least partially exposing the at least one via hole of the first intermetal dielectric layer. A second conductive interconnection layer is provided in the at least one via hole of the second intermetal dielectric layer that electrically contacts the first conductive interconnection layer.

Integrated circuit devices including a capacitor

Provided is a method of manufacturing a semiconductor device having a first region, in which a capacitance component is a dominant cause of a RC delay, and a second region, in which a resistance component is a dominant cause of a RC delay. The method comprises performing a first etching process to an insulating layer formed on a semiconductor substrate, so that a first trench having a first thickness and a second trench having the first thickness are formed in the first region and the second region, respectively; performing a second etching process to the second trench, so that a third trench having a second thickness thicker than the first thickness is formed in the second region; filling the first trench and the third trench with a metal layer; and removing portions of the metal layer, so that a first metal interconnection and a second metal interconnection are formed inside of the first trench and the third trench, respectively.

Method of manufacturing semiconductor device having metal interconnections of different thickness

Integrated circuit devices include an integrated circuit substrate and a conductive lower electrode layer of a Metal-Insulator-Metal (MIM) capacitor on the integrated circuit substrate. A dielectric layer is on the lower electrode layer and a conductive upper electrode layer of the MIM capacitor is on the dielectric layer. A first intermetal dielectric layer is on the upper electrode layer. The first intermetal dielectric layer includes at least one via hole extending to the upper electrode layer. A first conductive interconnection layer is on the at least one via hole of the first intermetal dielectric layer. A second intermetal dielectric layer is on the first intermetal dielectric layer. The second intermetal dielectric layer includes at least one via hole extending to the first conductive interconnection layer and at least partially exposing the at least one via hole of the first intermetal dielectric layer. A second conductive interconnection layer is provided in the at least one via hole of the second intermetal dielectric layer that electrically contacts the first conductive interconnection layer.

Integrated circuit devices including a MIM capacitor

A bond pad of a semiconductor device capable of restraining dishing and having improved conductivity by a damascene technique using a copper pattern, includes first and second copper patterns of irregular lattice models, first and second dielectric layer patterns to connect the first and second copper patterns in the vertical direction, a line connection structure horizontally connecting the first and second copper patterns, and a conductivity improving layer formed on the first and second copper patterns. Dishing generated in planarizing the first and second copper patterns by a damascene technique can be restrained due to the first and second copper patterns of the lattice models. Also, the conductivity property of the bond pad can be improved by connecting the first and second copper patterns horizontally and in the vertical direction and further forming the conductivity improving layer on the first and second copper patterns.

Bond pad of semiconductor device and method of fabricating the same

A semiconductor device having a dual damascene line structure and a method for fabricating the same are disclosed. The semiconductor device and the method solve the conventional problem of a partially, or fully, closed contact hole, and restrain increase in the parasitic capacitance in an interlayer insulation layer due to an increase in the dielectric constant thereof through the use of an etching stopper layer. To achieve this, a first interlayer insulation layer is formed on a semiconductor substrate on which a first conductive pattern is formed. Next, the etching stopper pattern having an etching selection ratio with respect to the first interlayer insulation layer is partially formed in a particular area. Thereafter, a second interlayer insulation layer and a second conductive layer made of copper are formed.

Growing community of inventors

Gwacheon, South Korea

Kyung-tae Lee