Samsung Electronics Co., Ltd.

Kyung-Tae Jang

Myoung-Bum Lee

Chang-Won Lee

Tae-Jong Han

Ji-Youn Seo

Yong-Chae Jung

Woong-hee Sohn

Shin-Jae Kang

Hyunseok Lim

Seung-Mok Shin

Tai-Soo Lim

Sang-Hoon Lee

Jin-Hong Kim

Myoungbum Lee

JinGyun Kim

Joon Hyuk Kim

Suk-chul Bang

Won-Seok Jung

Seung-Yup Lee

Yun-seung Kang

Jongmyeong Lee

Jiwoon Im

Yeon-Sil Sohn

Ju-Wan Kim

Seungmok Shin

Eun-Kuk Chung

Kwangchul Park

Daewoong Kim

Jongwan Choi

Byungho Chun

Koong-Hyun Nam

Ji-Woon Im

Ohchel Kwon

Jiyoun Seo

Hyun-Yong Go

Dae-Hun Choi

Jong-Seon Ahn

Hyung-Mo Yang

Chang-Yeon Yoo

Bongcheol Kim

A method for fabricating a semiconductor device includes forming a stacked structure on a substrate, forming a first interlayer dielectric covering the stacked structure, and forming a second interlayer dielectric covering the first interlayer dielectric. The stacked structure includes a stepwise shape. The first interlayer dielectric includes at least one step portion having a slope surface connecting a first top surface to a second top surface. The first top surface and the sloped surface define a first angle that is an obtuse angle. A level of the second top surface is higher than a level of the first top surface.

Method for fabricating semiconductor device including a first ILD with sloped surface on a stacked structure and a second ILD on the first ILD

In a method of a vertical memory device, insulation layers and sacrificial layers are alternately and repeatedly formed on a substrate. A hole is formed through the insulation layers and the sacrificial layers that expose a top surface of the substrate. Then, an interior portion of the hole may be enlarged. A semiconductor pattern is formed to partially fill the enlarged portion of the hole. A blocking layer, a charge storage layer and a tunnel insulation layer may be formed on a sidewall of the hole and the semiconductor pattern. Then, the tunnel insulation layer, the charge storage layer and the blocking layer are partially removed to expose a top surface of the semiconductor pattern. A channel is formed on the exposed top surface of the semiconductor pattern and the tunnel insulation layer. The sacrificial layers are replaced with gate electrodes.

Vertical memory devices and methods of manufacturing the same

Methods of manufacturing a three-dimensional semiconductor device are provided. The method includes: forming a thin film structure, where first and second material layers of at least 2n (n is an integer more than 2) are alternately and repeatedly stacked, on a substrate; wherein the first material layer applies a stress in a range of about 0.1&#xd7;109 dyne/cmto about 10&#xd7;109 dyne/cmto the substrate and the second material layer applies a stress in a range of about &#x2212;0.1&#xd7;109 dyne/cmto about &#x2212;10&#xd7;109 dyne/cmto the substrate.

Methods of manufacturing three-dimensional semiconductor memory devices

A semiconductor device includes a substrate, a plurality of insulating layers vertically stacked on the substrate, a plurality of channels arranged in vertical openings formed through at least some of the plurality of insulating layers, and a plurality of portions alternatingly positioned with the plurality of insulating layers in the vertical direction. At least some of the portions are adjacent corresponding channels of the plurality of channels. Each of the portions includes a conductive barrier pattern formed on an inner wall of the portion, a filling layer pattern positioned in the portion on the conductive barrier pattern, and a gate electrode positioned in a remaining area of the portion not occupied by the conductive barrier or filling layer pattern.

Methods of forming a semiconductor device include forming an insulation layer on a semiconductor structure, forming an opening in the insulation layer, the opening having a sidewall defined by one side of the insulation layer, forming a first metal layer in the opening, at least partially exposing the sidewall of the opening by performing a wet-etching process on the first metal layer, and selectively forming a second metal layer on the etched first metal layer. An average grain size of the first metal layer is smaller than an average grain size of the second metal layer. Related semiconductor devices are also disclosed.

Semiconductor device and method for forming the same

A vertical non-volatile memory device includes a semiconductor pattern disposed on a substrate; and a plurality of transistors of first through n-th layers that are stacked on a side of the semiconductor pattern at predetermined distances from each other, wherein the transistors are spaced apart and insulated from one another at the predetermined distances via air gap, where n is a natural number equal to or greater than 2.

Vertical non-volatile memory device

Methods of forming vertical nonvolatile memory devices utilize carbon-blocking sacrificial capping layers to increase device yield by reducing the likelihood that one or more vertically-stacked layers of materials will lift-off during fabrication. These capping layers may be provided to cover carbon-containing sacrificial layers that are highly polymerized.

Methods of forming semiconductor memory devices having vertically stacked memory cells therein

Semiconductor device and method of forming the same

In a semiconductor device and method of manufacturing the semiconductor device, a punch-through prevention film pattern and a channel film pattern are formed on an insulation layer. The punch-through prevention pattern and the insulation layer may include nitride and oxide, respectively. The punch-through prevention pattern is located under the channel pattern.

Semiconductor device and method of manufacturing the same

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Kyung-Tae Jang