Samsung Electronics Co., Ltd.

Kyung-Tae Do

Jung-Yun Choi

Hyo-Sig Won

Wook Hwan Kim

Jong-Ho Kim

Young-Hwan Kim

Yong-Seok Lee

Bong-hyun Lee

Bong-Hyun Lee

Jae-Han Jeon

In a method of designing a semiconductor device, a transistor included in a layout of the semiconductor device may be selected. A biasing data may be set for changing a characteristic of the selected transistor. A design rule check (DRC) process for the layout of the semiconductor device may be performed after ignoring the biasing data. An optical proximity correction (OPC) process for the layout of the semiconductor device may be performed based on the biasing data.

Methods of designing semiconductor devices and methods of modifying layouts of semiconductor devices

In a method of estimating a leakage current in a semiconductor device, a chip including a plurality of cells is divided into segments by a grid model. Spatial correlation is determined as spatial correlation between process parameters concerned with the leakage currents in each of the cells. A virtual cell leakage characteristic function of a cell is generated by arithmetically operating actual leakage characteristic functions. A segment leakage characteristic function of a segment is generated by arithmetically operating the virtual cell leakage characteristic functions of all cells in the segment. Then, a full chip leakage characteristic function of the chip is generated by statistically operating the segment leakage characteristic functions of all segments in the chip. Accordingly, computational loads of Wilkinson's method for generating the full chip leakage characteristic function can remarkably be reduced.

Method of estimating a leakage current in a semiconductor device

A circuit having an active clock shielding structure includes a logic circuit that receives a clock signal and performs a logic operation based on the clock signal, a power gating circuit that switches a mode of the logic circuit between an active mode and an sleep mode based on a power gating signal, a clock signal transmission line that transmits the clock signal to the logic circuit, and at least one power gating signal transmission line that transmits the power gating signal to the power gating circuit and functions as a shielding line pair with the clock signal transmission line.

Circuit having an active clock shielding structure and semiconductor intergrated circuit including the same

Growing community of inventors

Gyeongsangnam-do, South Korea

Kyung-Tae Do