Rambus Inc.

Altera Corporation

Kyung Suk Oh

Ian P Shaeffer

Brian S Leibowitz

David A Secker

Hae-Chang Lee

Akash Bansal

Wayne S Richardson

Lawrence Lai

Fan Ho

Jihong Ren

Jared L Zerbe

Qi Lin

Ralf M Schmitt

Lei Luo

Yijiong Feng

Huy M Nguyen

John M Wilson

Yu Chang

Eugene C Ho

Woopoung Kim

Tim Tri Hoang

Frank Lambrecht

David Nguyen

Sean Shau-Tu Lu

Yujeong Shim

Guang Chen

Joong-Ho Kim

Frederick Abbott Ware

Sergey Yuryevich Shumarayev

Arifur Rahman

Weiqi Ding

Yohan Usthavia Frans

Jade M Kizer

Kaushik Chanda

Yanzhong Xu

Hui Liu

Boon Jin Ang

Ravindranath T Kollipara

Pravin Kumar Venkatesan

John Cronan Eble, Iii

Chi-Ming Yeung

Xiaohong Jiang

Yanjing Ke

Loke Yip Foo

Wai Ling Lee

Karthik Chandrasekar

Charu Sardana

Yee Huan Yew

Sunitha Chandra

Mei See Chin

Nathaniel Wright Unger

Chee Cheong Tan

Chooi Ian Loh

Hui Lee Teng

Heetae Ahn

WooPoung Kim

Yijong Feng

John Wilson

Shaeffer Ian P P

John Cronan Eble

In an integrated circuit component having a command interface to receive commands, a data interface to receive write data during a write-data reception interval, and first and second registers, control circuitry within the integrated circuit component responds to one or more of the commands by storing within the first register and the second register, respectively, a first control value that specifies a first termination to be applied to the data interface during the write-data reception interval, and a second control value that specifies a second termination to be applied to the data interface after the write-data reception interval transpires.

Integrated circuit that applies different data interface terminations during and after write data reception

A memory device includes a set of inputs, and a first register that includes a first register field to store a value for enabling application of one of a plurality of command/address (CA) on-die termination (ODT) impedance values to first inputs that receive the CA signals; and a second register field to store a value for enabling application of one of a plurality of chip select (CS) ODT impedance values to a second input that receives the CS signal. A third register field may store a value for enabling application of a clock (CK) ODT impedance value to third inputs that receive the CK signal.

On-die termination of address and command signals

A structure for delivering power is described. In some embodiments, the structure can include conductors disposed on two or more layers. Specifically, the structure can include a first set of interdigitated conductors disposed on a first layer and oriented substantially along an expected direction of current flow. At least one conductor in the first set of interdigitated conductors may be maintained at a first voltage, and at least one conductor in the first set of interdigitated conductors may be maintained at a second voltage, wherein the second voltage is different from the first voltage. The structure may further include a conducting structure disposed on a second layer, wherein the second layer is different from the first layer, and wherein at least one conductor in the conducting structure is maintained at the first voltage.

Structure for delivering power

A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.

Memory device comprising programmable command-and-address and/or data interfaces

A memory device includes a set of inputs, and a first register that includes a first register field to store a value for enabling application of one of a plurality of command/address (CA) on-die termination (ODT) impedance values to first inputs that receive the CA signals; a second register field to store a value for enabling application of one of a plurality of chip select (CS) ODT impedance values to a second input that receives the CS signal; and a third register field to store a value for enabling application of a clock (CK) ODT impedance value to third inputs that receive the CK signal. The memory device also includes second and third registers to store values for selecting one of the plurality of CA ODT impedance values and one of the plurality of CS ODT impedance values for application to the first inputs and second input, respectively.

A system has a plurality of memory devices arranged in a fly-by topology, each having on-die termination (ODT) circuitry for connecting to an address and control (RQ) bus. The ODT circuitry of each memory device includes a set of one or more control registers for controlling on-die termination of one or more signal lines of the RQ bus. A memory controller sends register values, for storage in a plurality of registers of a respective memory device. The register values include register values that represent one or more impedance values of on-die termination (ODT) impedances to apply to the respective inputs of the respective memory device that receive the CA signals, and one or more register values to selectively enable application of a chip select ODT impedance to the chip select input of the respective memory device.

A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.

Receiver with clock recovery circuit and adaptive sample and equalizer timing

A memory control component outputs a memory write command to a memory IC and also outputs write data to be received via data inputs of the memory IC. Prior to reception of the write data within the memory IC, the memory control component asserts a termination control signal that causes the memory IC to apply to the data inputs a first on-die termination impedance during reception of the write data followed by a second on-die termination impedance after the write data has been received. The memory control component deasserts the termination control signal to cause the memory IC to apply no termination impedance to the data inputs.

On-die termination control

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Cupertino, CA, United States of America

Kyung Suk Oh