Samsung Electronics Co., Ltd.

Kyung-soo Kim

Kyoo-chul Cho

Young-Wug Kim

Sam-jong Choi

Chang-bong Oh

Hee-sung Kang

Tae-soo Kang

Jae-ryong Jung

Hyuk-ju Ryu

Sang-Sig Kim

Yong-kwon Kim

Hee-Sung Kang

Mu-kyeng Jung

Hyuk-Ju Ryu

Jae-sang Park

Yong-in Ko

Woo-young Chung

Jae-bum Park

Methods of forming a gate structure for an integrated circuit memory device include forming a first dielectric layer having a dielectric constant of under 7 on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm/s) are injected into the first dielectric layer to form a charge storing region in the first dielectric layer with a tunnel dielectric layer under the charge storing region. A metal oxide second dielectric layer is formed on the first dielectric layer, the second dielectric layer. The substrate including the first and second dielectric layers is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region and a gate electrode layer is formed on the second dielectric layer. Gate structures for integrated circuit devices and memory cells are also provided.

Integrated circuit device gate structures

Methods of forming integrated circuit device gate structures

In a method for manufacturing a multi-thickness gate dielectric layer of a semiconductor device, a first dielectric layer is formed on a semiconductor substrate. A second dielectric layer is formed using a different dielectric material from the material constituting the first dielectric layer on the first dielectric layer. A portion of the second dielectric layer is selectively removed so as to selectively expose the first dielectric layer under the second dielectric layer. A portion of the exposed first dielectric layer is selectively removed so as to selectively expose the semiconductor substrate under the exposed first dielectric layer. Thereafter, a third dielectric layer having a thinner thickness than the first dielectric layer is formed on the exposed semiconductor substrate. As a result, a gate dielectric layer is formed to include a thick portion formed of the first dielectric layer and remaining second dielectric layer, a medium-thickness portion formed of the remaining first dielectric layer, and a thin portion formed of the third dielectric layer.

Method for manufacturing multi-thickness gate dielectric layer of semiconductor device

A complementary metal oxide semiconductor (CMOS) device having improved performance includes a first device active region including at least one pair of transistor active regions wherein one transistor active region has a first width and the other transistor active region for forming a contact has a second width, a first gate arranged on the first device active region, a MOS transistor of a first conductivity type including a source/drain region of the first conductivity type formed in the first device active region, a second device active region having a third width greater than the first width, a second gate arranged on the second device active region, and a MOS transistor of a second conductivity type including a source/drain region of the second conductivity type formed in the second device active region.

CMOS device with improved performance and method of fabricating the same

An apparatus and method for carrying wafers through a multi-step process for producing a semiconductor, without using a cassette, where the apparatus senses whether a wafer is mis-loaded. The apparatus includes a plurality of optical sensors positioned above the wafers for sensing whether a wafer is mis-loaded by transmitting light past circumferential edges of the wafers.

Semiconductor manufacturing device including sensor for sensing

Growing community of inventors

Gyeonggi-do, South Korea

Kyung-soo Kim