Samsung Electronics Co., Ltd.

Kyung-Soo Ha

Chang-Kyo Lee

Ki-Seok Oh

Jung-Hwan Choi

Seok-Hun Hyun

Yeon-Kyu Choi

Dae-Sik Moon

Young-Hoon Son

Si-hong Kim

Tae-Young Oh

Gil-Hoon Cha

Young-Soo Sohn

Young-hun Kim

Donghun Lee

Changkyo Lee

Jin-Hoon Jang

Hyun-Yoon Cho

Daesik Moon

Seokhun Hyun

Sungchul Park

Sanguhn Cha

Hyong-Ryol Hwang

Kiheung Kim

Hyojin Jung

Young-Hwa Kim

Jin-Hun Jang

Seung-Jun Bae

Dae-hyun Kim

Taeyoung Oh

Woo-Jin Lee

Junhyung Kim

Jun Hyung Kim

Seong-Hwan Jeon

Chang-Yong Lee

In-Dal Song

Sihong Kim

Ho-Seok Seol

Ki-Heung Kim

Jung-Hwan Park

JunHyung Kim

Jin-Seok Heo

Seok-Jin Cho

Sang Uhn Cha

Dong-Keon Lee

Hyung-Joon Chi

There are provided a memory device for supporting a command bus training (CBT) mode and a method of operating the same. The memory device is configured to enter a CBT mode or exit from the CBT mode in response to a logic level of a first data signal, which is not included in second data signals, which are in one-to-one correspondence with command/address signals, which are used to output a CBT pattern in the CBT mode. The memory device is further configured to change a reference voltage value in accordance with a second reference voltage setting code received by terminals associated with the second data signals, to terminate the command/address signals or a pair of data clock signals to a resistance value corresponding to an on-die termination (ODT) code setting stored in a mode register, and to turn off ODT of data signals in the CBT mode.

Memory device for supporting command bus training mode and method of operating the same

A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.

Memory device, memory system, and operation method of memory device

A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register, a scrubbing control circuit and a control logic circuit. The memory cell array includes memory cell rows. The scrubbing control circuit generates scrubbing addresses based on refresh operations performed on the memory cell array. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection operation on a plurality of sub-pages in a first memory cell row to count a number of error occurrences, and determines whether to correct a codeword in which an error is detected based on the number of error occurrences. An uncorrected or corrected codeword is written back, and a row address of the first memory cell row may be stored in the fault address register as a row fault address based on the number of error occurrences.

Semiconductor memory devices and methods of operating semiconductor memory devices

A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

Memory device adjusting duty cycle and memory system having the same

A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.

Method and memory system for optimizing on-die termination settings of multi-ranks in a multi-rank memory device

A method of operating a memory device is provided. The method includes: receiving a first command from a controller; activating a page of a memory cell array based on the first command; reading data of the activated page; detecting an error from the read data; correcting the detected error to generate error correction data; writing back the error correction data to the activated page in based on the detected error being a single-bit error; and blocking write-back of the error correction data to the activated page based on the detected error being a multi-bit error.

Method of operating memory device, method of operating memory controller and memory system

A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.

Method of controlling on-die termination and system performing the same

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Hwaseong-si, South Korea

Kyung-Soo Ha