Skhynix Inc.

Kyung Sik Mun

Hee Youl Lee

Se Jun Kim

Moon Sik Seo

A semiconductor memory device is provided. The semiconductor memory device includes memory strings including drain-side memory cells connected between a bit line and a pipe transistor, and source-side memory cells connected between the pipe transistor and a source line, and a peripheral circuit suitable for applying a pipe gate voltage to a pipe gate of the pipe transistor before applying pass voltages to turn on non-selected memory cells among the drain-side memory cells and the source-side memory cells during a read operation.

Semiconductor memory device having memory strings including drain-side and source-side memory cells connected to pipe transistor and peripheral circuit suitable for applying pipe gate voltage to pipe transistor during read operation

The semiconductor device includes a CAM block including a plurality of vertical strings having a perpendicular configuration with respect to a semiconductor substrate, wherein each of the plurality of vertical strings is electrically coupled to a plurality of word lines and each of the plurality of word lines is electrically coupled to a plurality of CAM cells, a peripheral circuit configured to program CAM cells selected from the plurality of CAM cells, and a control circuit configured to issue at least one command to the peripheral circuit to simultaneously apply a program voltage to an nword line, an n&#x2212;1word line and an n+1word line to simultaneously program CAM cells electrically coupled to the n&#x2212;1word line, the nword line and the n+1word line, wherein the n&#x2212;1word line and an n+1word line are adjacent to the nword line and the selected CAM cells are electrically coupled to the nword line.

Semiconductor device and operating method thereof

An operating method of a semiconductor device is provided. The operating method of the semiconductor memory device includes programming a second source select transistor electrically coupled to a common source line through a first source select transistor; reprogramming the second source select transistor when a threshold voltage of the second source select transistor is less than a target voltage, and ending a program for the second source select transistor when the threshold voltage of the second source select transistor is greater than or equal to the target voltage. The programming includes electrically decoupling the second source select transistor from the common source line by turning off the first source select transistor.

Semiconductor memory device and operating method thereof

The semiconductor memory device includes a memory cell array including a plurality of cell transistors, and a page buffer configured to perform an verification operation for verifying a program state of a selected cell transistor by sensing a voltage of a sense node connected to a selected bit line of the memory cell array through a bit line selection transistor, wherein a logic level corresponding to a voltage of the selected bit line is constantly maintained regardless of the program state of the selected cell transistor during the verification operation.

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Gyeonggi-do, South Korea

Kyung Sik Mun