Samsung Electronics Co., Ltd.

Seoul National University

Kyung-seok Oh

Joo-Sung Park

Jung-Hyun Shin

Min-sung Kang

Ki-Jae Hur

Yang-koo Lee

Byung-Gook Park

In-gyu Baek

Young-Hoon Park

Kyung-Chang Ryoo

Young-hoon Park

Seung-ku Lee

Myoung-seob Shim

Jeong-hoon Oh

Hun-chul Shin

Example embodiments disclose a semiconductor device using resistive memory material layers and a method of driving the semiconductor device. The semiconductor device includes a plurality of memory cells. At least one memory cell includes a uni-polar variable resistor and a bi-polar variable resistor connected in series and configured to switch between low resistance states and high resistance states, respectively, according to an applied voltage.

Semiconductor devices and methods of driving the same

A semiconductor fuse box includes a fuse structure and a protective structure disposed between the fuse structure and an integrated circuit structure. The protective structure has at least one irregular side surface. The protective structure (which may also include a pad formed there-under) extends beyond a bottom of the fuse structure. Such an irregular side surface and such an extension of the protective structure minimize propagation of damaging energy to the adjacent integrated circuit structure when a laser beam is directed to the fuse structure.

Semiconductor fuse box and method for fabricating the same

A field effect transistor includes a channel region under a gate stack formed on a semiconductor structure. The field effect transistor also includes a drain region formed with a first dopant doping a first side of the channel region, and includes a source region formed with the first dopant doping a second side of the channel region. The drain and source regions are doped asymmetrically such that a first charge carrier profile between the channel and drain regions has a steeper slope than a second charge carrier profile between the channel and source regions.

Methods of forming an asymmetric field effect transistor

Asymmetric field effect transistor

A CMOS integrated circuit includes an NMOS transistor and a PMOS transistor in an integrated circuit substrate. The NMOS transistor and the PMOS transistor each include a gate, and a source/drain on opposing sides of the gate. An insulating layer is located on the integrated circuit substrate. The insulating layer includes a contact hole therein which exposes a portion of a corresponding one of the source/drains. A source/drain plug is formed in the corresponding one of the source/drains. The source/drain plug is of opposite conductivity from the corresponding one of the source/drains. The source/drain plug is centered about the portion of the corresponding one of the source/drains. The source/drain plug may be formed by ion implantation through the contact hole and is thereby self-aligned to the contact hole. The source/drain plug can compensate for misalignment and the diffusion for highly integrated CMOS devices.

Methods for fabricating CMOS integrated circuits including source/drain compensating regions

CMOS integrated circuits including source/drain plug

A method for forming an opening in an integrated circuit device with an improved aspect ratio includes the following steps. An inter-insulating layer is formed on a surface of a substrate. A recess having a first width is then formed in the inter-insulating layer. Next, a hole having a second width is formed in the inter-insulating layer at a base of the recess, wherein the first width is greater than the second width. Thus, an opening is formed to have a cross-sectional shape of a step where its upper portion formed by the recess which is wider than its lower portion formed by the hole. Accordingly, open circuits caused by voids formed in the opening in subsequent metal deposition steps may be prevented.

Methods for forming openings with improved aspect ratios in integrated

A method for forming contact holes having different depths in an insulating layer which covers a semiconductor substrate. A first step selectively etches the upper parts of the insulating layer which correspond to contact holes having a greater depth than the shallowest contact hole, using a first mask pattern. A second etch step selectively etches the remainder of the insulating layer for all of the contact holes at the same time using a second mask pattern. Thus, contact hole misalignment is kept to a minimum.

Method for forming contact holes having different depths

Growing community of inventors

Seongnam-si, South Korea

Kyung-seok Oh