Samsung Electronics Co., Ltd.

Kyung-Ryun Kim

Sang-Yong Yoon

Young-Hun Seo

Hyung-Jin Kim

Jang-Woo Ryu

Hui-Kap Yang

Yoon-Na Oh

Sang-Uhn Cha

Hyun-chul Yoon

Ki-Tae Park

Ki-Whan Song

Kyung-ho Kim

Jin-Young Chun

Joon-Suc Jang

Si-Hwan Kim

Jin-yong Choi

Sang-kwon Moon

Woong-dai Kang

Dong-sub Kim

A method includes replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block, and reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device.

Semiconductor memory devices, memory systems, and methods of operating semiconductor memory devices

A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit, and a control logic circuit. The memory cell array includes a plurality of bank arrays, and each of the bank arrays includes dynamic memory cells. The control logic circuit generates a first control signal to control the I/O gating circuit and a second control signal to control the ECC engine, in response to an access address and a command. The control logic circuit controls the ECC engine to perform s-bit ECC encoding on a write data to be stored in a first page of at least one bank array, in response to a first command, and controls the ECC engine to perform t-bit ECC decoding on a first codeword read from the first page, in response to a second command.

Semiconductor memory devices, memory systems, and methods of operating the semiconductor memory devices

A sense amplifier includes a first sense amplification circuit electrically connected between a bit line, to which a multi-bit memory cell is also connected, and a complementary bit line. The first sense amplification circuit is configured to sense a least significant bit (LSB) of 2-bit data in the memory cell and latch the LSB in a first sensing bit line pair. A second sense amplification circuit is provided, which is configured to sense a most significant bit (MSB) of the 2-bit data and latch the MSB in a second sensing bit line pair. A switching circuit is provided, which is configured to selectively connect between bit lines of the first sensing bit line pair and bit lines of the second sensing bit line pair.

Sense amplifier for sensing multi-level cell and memory device including the sense amplifer

Sense amplifier for sensing multi-level cell and memory device including the sense amplifier

A semiconductor memory device a memory cell array and a repair control circuit. The memory cell array including a normal cell region and a redundancy cell region, the normal cell region including a plurality of normal region groups, and redundancy cell region configured to replace failed memory cells of the normal cell region. The repair control circuit configured to, determine a target normal region group from among the plurality of normal region groups based on an input address, extract target fail addresses from among a plurality of fail addresses based on the target normal region group, and control a repair operation based on the target fail addresses and the input address.

Semiconductor memory device and method of operating the same

A memory device including a memory cell array connected to a first bit line, first word lines, and second word lines, the memory cell array including a first memory cell and a second memory cell, the first memory cell being connected between the first word lines and the first bit line, and the second memory cell being connected between the second word line and the first bit line; a first word line driver configured to drive the first word lines; a second word line driver configured to drive the second word lines; and a test manager configured to drive second word lines to change a capacitance of the first bit line, and after the capacitance of the first bit line is changed, drive first word lines to test the first word lines.

Memory device performing test on memory cell array and method of operating the same

A semiconductor memory device may include a memory cell array and an access control circuit. The memory cell array may include a first cell region and a second cell region. The access control circuit may access the first cell region and the second cell region differently in response to a command, an access address and fuse information to identify the first cell region and the second cell region. The command and the address may be provided from an external device.

Semiconductor memory devices, methods of operating semiconductor memory devices and memory systems

A memory diagnosis system includes a memory device and a server. The memory device includes a memory module configured to adjust operational parameters in response to a parameter control signal, a memory controller configured to generate the parameter control signal in response to a feedback signal, and a memory state monitor configured to monitor the memory module to generate an information signal that includes information on a state of the memory module. The server is configured to generate the feedback signal in response to the information signal.

Memory diagnosis system

A method of operating a memory system, including a memory device, includes managing program order information of the memory device based on a program order stamp (POS) indicating a relative temporal relationship between program operations of a plurality of memory groups that are included in the memory device. The method includes generating a first mapping table that stores a read voltage offset and an upper POS corresponding to the read voltage offset, by using a plurality of voltage levels that are sequentially decreased or reduced, and generating a second mapping table that stores the read voltage offset and a lower POS corresponding to the read voltage offset, by using a plurality of voltage levels that are sequentially increased. A read voltage for performing a read operation on the memory device is variably determined based on the first and second mapping tables and the program order information.

Memory system and method including determining a read voltage based on program order information and a plurality of mapping tables

A method of operating a memory system includes managing program order information of the memory device based on program order stamps (POSs) indicating relative temporal relationships between program operations performed in relation to a plurality of memory groups included in the memory device, and controlling operations directed to the plurality of memory groups in response to the program order information.

Memory system and method of operating same using program order information

A flash memory, a flash memory system, and an operating method thereof. The method of operating a flash memory includes counting the number of memory cells having threshold voltages included in a first adjacent threshold voltage range (defined by a first reference read voltage for distinguishing between initially separated adjacently located threshold voltage distributions and a first search read voltage having a first voltage difference from the first reference read voltage), and a second adjacent threshold voltage range (defined by the first reference read voltage and a second search read voltage having a second voltage difference from the first reference read voltage), and setting a first optimal read voltage based on the difference between the first and second counted numbers of the memory cells.

Flash memory, flash memory system and operating method of the same

In a method of reading a memory device, difference information is generated based on a distance difference between a position of a read word-line and a position of a boundary word-line. The read word-line corresponds to a read address. The boundary word-line corresponds to a last programmed word-line in a memory block included in a memory cell array. A read word-line voltage and an adjacent word-line voltage are determined based on the difference information. The read word-line voltage is applied to the read word-line. The adjacent word-line voltage is applied to an adjacent word-line that is adjacent to the read word-line. A read data corresponding to the read address is outputted based on the read word-line voltage and the adjacent word-line voltage. The read method of the memory device according to example embodiments may be capable of increasing the performance by controlling the voltages applied to the adjacent word-line and the read word-line according to the difference information determined based on the read word-line and the boundary word-line.

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Seoul, South Korea

Kyung-Ryun Kim