Hynix Semiconductor Inc.

Kyung Pil Hwang

Min Kyu Lee

Seok Jin Joo

Hyung Seok Kim

Ju In Kim

Keum Hwan Noh

Sook Kyung Kim

Won Sic Woo

Ki Hong Lee

Jung Ryul Ahn

Eun Seok Choi

Se Jun Kim

Ki Seon Park

Hyun Seung Yoo

Young Ok Hong

Kyoung Hwan Park

Moon Sig Joo

Myung Shik Lee

Yong Top Kim

Jae Young Park

Seoung Ouk Choi

A method of erasing and programming a flash memory device including multi-level cells (MLCs). MLCs of a word line are selected and some of the MLCs are pre-programmed based on whether their individual threshold voltages are included in a first voltage range. The selected MLCs are pre-programmed with a pre-program (first) voltage; and the remaining MLCs are prohibited from pre-programming; then the remaining MLCs connected to the selected word line are programmed by applying a program (second) voltage that gradually rises from the pre-program voltage at a ratio of a step voltage n for the selected line.

Program method of flash memory device

Erase and program methods of a flash memory device including MLCs for increasing the program speed. In the erase method, MLCs are pre-programmed so that a voltage range in which threshold voltages of MLCs are distributed can be reduced. Therefore, a fail occurrence ratio can be reduced when erasing MLCs, the threshold voltage distribution of MLCs can be improved and an overall program time can be shortened in a subsequent program operation.

Erase method of flash memory device

A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer.

Nonvolatile memory device and method of fabricating the same

A non-volatile memory device is provided. In an aspect, the non-volatile memory device includes two or more common source lines that are included in one memory cell block in order to distribute the current that could have been concentrated on one common source line. As a result, the bouncing phenomenon generated by the nose of the source line can be reduced. That is, at the time of a verifying operation performed during a program operation, the current concentrated on a common source line can be distributed and, therefore, the occurrence of under-programmed cells can be prevented.

Non-volatile memory device

Erase and program methods of a flash memory device including MLCs for increasing the program speed are described. In the erase method, MLCs are pre-programmed so that a voltage range in which threshold voltages of MLCs are distributed can be reduced. Therefore, a fail occurrence ratio can be reduced when erasing MLCs, the threshold voltage distribution of MLCs can be improved and an overall program time can be shortened in a subsequent program operation.

Erase and program method of flash memory device for increasing program speed of flash memory device

The present invention relates to a method of forming a dual junction region and a method of forming a transfer transistor using the same. A low-concentration junction region is formed. A high-concentration junction region is formed at a portion of the low-concentration junction region by performing a high-concentration ion implantation process an ion implantation mask for an interlayer dielectric film in which a contact hole is formed so that the portion of the low-concentration junction region is exposed. With this structure, the distance between the high-concentration junction region and the well is sufficiently secured by controlling the distance between the high-concentration junction region and the well using the width of the contact hole formed in the interlayer dielectric film. Therefore, a stable characteristic can be secured upon application of a subsequent high voltage bias.

Method of forming double junction region and method of forming transfer transistor using the same

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Seoul, South Korea

Kyung Pil Hwang