Samsung Electronics Co., Ltd.

Kyung-min Kim

Young-Bae Kim

Chang-jung Kim

Man Chang

Seung-ryul Lee

Yong Kyun Lim

Kyoung Min Koh

Kyoung-Min Koh

Eun-ju Cho

Sung-Ho Kim

Jin Woo Kim

Jin-Woo Kim

Myoung-jae Lee

Dong-Soo Lee

Chang-bum Lee

Byung-jo Kim

Sae-jin Kim

Donghyun Kim

Seog Heon Ham

Tae Chan Kim

Tae-Chan Kim

Min-Sun Keel

Hee Sung Chae

Young-Kyun Jeong

Hoyong Na

Mira Lee

Shinyeol Choi

Hae-sick Sul

Kyung Min Shin

Chanho Chun

Yoon-seok Han

Yoon-Seok Han

June Soo Han

Myoung Su Lee

An image sensor includes a pixel array that includes a plurality of pixels, and a row driver. Each pixel includes a photodiode, a transfer gate transistor between the photodiode and a floating diffusion node, and a first transistor between the floating diffusion node and a first voltage node configured to receive a first voltage. The row driver is connected with rows of the pixels through row lines. For each pixel of a selected row among the rows, the row driver is configured to apply a second voltage to a gate of the first transistor such that the first transistor is turned on and the floating diffusion node is reset, and turn on the transfer gate transistor such that electrons integrated in the photodiode are dumped to the floating diffusion node.

Image sensor, camera module including image sensor, and operating method of image sensor

Disclosed is an image sensor including a pixel array including a plurality of pixels, each of the pixels including a first photodiode and a second photodiode, each of which outputs a first pixel signal based on a first conversion gain using the second photodiode in a first period, outputs a second pixel signal based on a second conversion gain using the second photodiode in a second period, outputs a third pixel signal based on the first conversion gain using the first photodiode in a third period, and outputs a fourth pixel signal based on the second conversion gain using the first photodiode in a fourth period, an ADC circuit that performs sampling on a reset signal and an image signal of each of the first to fourth pixel signal. A sampling count and the number of sampling bits are adjusted differently from each of the first to fourth period.

Image sensor performing selective multiple sampling and operating method thereof

A counter includes a buffer unit and a ripple counter. The buffer unit generates at least one least significant signal of a count by buffering at least one clock signal until a termination time point. The ripple counter generates at least one most significant signal of the count by sequentially toggling in response to at least one of the least significant signal. The counter performs multiple data rate counting with enhanced operation speed and reduced power consumption.

Multiple data rate counter, data converter including the same, and image sensor including the same

A memory device may include a first electrode and a second electrode spaced apart from the first electrode. The memory device may further include a memory element disposed between the first electrode and the second electrode and a switching element disposed between the first electrode and the second electrode. The switching element may be configured to control signal access to the memory element. The memory device may further include a barrier layer disposed between the memory element and the switching element, the barrier layer including an insulation material.

Memory device and apparatus including the same

A resistive switching device includes a first material layer between a first electrode and a second electrode. The first material layer has a first region and a second region parallel to the first region. The first region corresponds to a conducting path formed in the first material layer, and is configured to switch from a low-resistance state to a high-resistance state in response to an applied voltage that is greater than or equal to a first voltage. The second region is configured to switch to a first resistance value that is less than a resistance value of the first region in the high-resistance state when the applied voltage is greater than or equal to a second voltage. The first region remains constant or substantially constant when the second region has the first resistance value.

Resistive switching devices and memory devices including the same

The image sensor includes a plurality of column lines, a plurality of active road circuits and a selection circuit. The plurality of column lines are each connected to a corresponding one of a plurality of pixels. The plurality of active road circuits are each connected to a corresponding one of the plurality of column lines. The selection circuit is configured to enable a portion of the plurality of active road circuits based on a plurality of column selection signals.

Image sensor, method for operating thereof, and image pick-up device having the same

An image sensor supporting a normal sampling mode and a 1/N sampling mode for transmitting image data detected by a plurality of unit image sensors and stored in a plurality of latch circuits to a data processor using a plurality of transmission lines, wherein N is a natural number greater than 2, the image sensor including a horizontal address generator configured to generate horizontal addresses corresponding to addresses of the plurality of latch circuits, and to generate, based on the horizontal addresses, a first channel selection control signal and a second channel selection control signal of which activation times at least partially overlap.

Image data processing method, image sensor and image data processing system using the method

According to example embodiments, a resistance switching material element includes a resistance switching material layer between a first electrode and a second electrode, and a self-rectifying layer provided between the resistance switching material layer and one of the first and second electrodes. The second electrode may be on the first electrode.

Resistance switching material element and device employing the same

An image sensor includes multiple counters and a counter controller. Each counter of the multiple counters is configured to perform counting of a comparison result signal and to generate a count result, the comparison result signal being obtained by comparing a ramp signal and a pixel signal of a column of multiple columns. The counter controller is configured to generate and transmit a counter clock signal and (n&#x2212;1) delay clock signals to the counters, respectively, 'n' being a natural number equal to or greater than two. Each delay clock signal of the (n&#x2212;1) delay clock signals is obtained by delaying the counter clock signal by a corresponding offset code.

Image sensor using offset code for counting

A two-terminal switching device includes a resistive switching element, a diode, and a resistive circuit. The resistive switching element switches between low and high resistance states based on a switching signal and maintain a switched resistance state until another switching signal is received. The diode is connected to the resistive switching element and blocks the switching signal from being transmitted to an output terminal. The resistive circuit allows the switching signal blocked by the diode to flow to the reference potential.

2-terminal switching device

In a method of operating a semiconductor device, a resistance value of a variable resistance element is changed from a first resistance value to a second resistance value by applying a first voltage to the variable resistance element; and a first current that flows through the variable resistance element is sensed. A second voltage for changing the resistance value of the variable resistance element from the second resistance value to the first resistance value is modulated based on a dispersion of the first current, and the first voltage is re-applied to the variable resistance element based on a dispersion of the first current.

Semiconductor devices including variable resistance elements and methods of operating semiconductor devices

A counter includes a buffer unit and a ripple counter. The buffer unit generates at least one least significant signal of a count by buffering at least one clock signal until a termination time point. The ripple counter generates at least one most significant signal of the count by sequentially toggling in response to at least one of the least significant signal. The counter performs multiple data rate counting with enhance operation speed and reduced power consumption.

An analog-to-digital converter (ADC) within an image sensor includes a comparator comparing a ramp signal with an image signal, and a counter generating a count result in response to the comparison by counting a clock during a counting interval. The ADC determines whether a first counting interval for the counter is less than a reference interval, and if the first counting interval is less than the reference interval the counting interval is a first counting interval, else the counting interval is a second counting interval.

Analog-to-digital converter using variable counting interval and image sensor including same

A method of driving a nonvolatile memory device including applying a reset voltage to a unit memory cell, reading a reset current of the unit memory cell, confirming whether the reset current is within a first current range, if the reset current is not within the first current range, changing the reset voltage and applying a changed reset voltage or applying again the reset voltage to the unit memory cell after applying a set voltage to the unit memory cell, if the reset current is within the first current range, confirming whether a difference between the present reset current and an immediately previous set current is within a second current range, and, if the difference is not within the second current range, applying the reset voltage or applying again the reset voltage to the unit memory cell after applying a set voltage to the unit memory cell.

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Suwon-si, South Korea

Kyung-min Kim