Samsung Electronics Co., Ltd.

Lg Electronics Inc.

Kyung Jun Shin

Ji Hye Kim

Byoung Il Lee

Dong Seog Eun

Hyun Kook Lee

Hyun Soo Kim

Seong Soon Cho

Joong Shik Shin

Dong Heon Shin

Hyun Sang Park

Sun Yup Kim

Jae Joo Shim

An embodiment of the present disclosure is a virtual home service apparatus including, a communicator, a home information collector for obtaining a design drawing of the home, and obtaining a 3D drawing by converting the design drawing, a home appliance identifier for obtaining an internal image and SLAM information of the home, and identifying the location and state of the home appliance based on the internal image and the SLAM information, and a virtual home implementator for generating virtual home information by reflecting the location and state of the home appliance to the 3D drawing. One or more among an autonomous driving vehicle, a user terminal, and a server according to an embodiment of the present disclosure may be associated with or converged with an Artificial Intelligence module, an Unmanned Aerial Vehicle (UAV), a robot, an Augmented Reality (AR) apparatus, a Virtual Reality (VR), 5G service-related apparatus, etc.

Apparatus and method for virtual home service

A vertical memory device includes a substrate having a cell array region and a connection region positioned on an exterior of the cell array region. Gate electrode layers are stacked on the cell array region and the connection region of the substrate, forming a stepped structure in the connection region. Channel structures are disposed in the cell array region, extending in a direction perpendicular to an upper surface of the substrate, while passing through the gate electrode layers. Dummy channel structures are disposed in the connection region, extending in the same direction as the channel structures, while passing through the gate electrode layers forming the stepped structure. First semiconductor patterns are disposed below the channel structures, and second semiconductor patterns are disposed below the dummy channel structures. The first and second semiconductor patterns include polycrystalline semiconductor materials.

Vertical memory device

A semiconductor device includes gate electrodes and interlayer insulating layers alternately stacked on a substrate, a channel layer penetrating through the gate electrodes and the interlayer insulating layers, and a gate dielectric layer disposed on an external surface of the channel layer between the gate electrodes and the channel layer. In addition, the channel layer includes a first region extended in a direction perpendicular to a top surface of the substrate and a second region connected to the first region in a lower portion of the first region and including a plane inclined with respect to the top surface of the substrate.

Semiconductor device

A vertical memory device is provided as follows. A substrate has a cell array region and a connection region adjacent to the cell array region. A first gate stack includes gate electrode layers spaced apart from each other in a first direction perpendicular to the substrate. The gate electrode layers extends from the cell array region to the connection region in a second direction perpendicular to the first direction to form a first stepped structure on the connection region. The first stepped structure includes a first gate electrode layer and a second gate electrode layer sequentially stacked. The second gate electrode layer includes a first region having the same length as a length of the first gate electrode layer and a second region having a shorter length than the length of the first gate electrode layer.

Growing community of inventors

Seoul, South Korea

Kyung Jun Shin