Palogen, Inc.

Nexflash Technologies, Inc.

Actel Corporation, Inc.

Gatefield Corporation

Other

Kyung Joon Han

Jack Zezhong Peng

Robert M Salter, Iii

Jungkee Yoon

Joo Weon Park

Steve K Hsia

Robert U Broze

Jong Seuk Lee

Gyu-Wan Kwon

Dung Tran

Victor Levchenko

Sung-Rae Kim

Volker Hecht

Robert Broze

Bita Karimirad

Nigel Chan

John L McCollum

Steven W Longcor

Eungjoon Park

Robert J Lipp

Poongyeub Lee

Robert V Broze

Imran Ali

Kang-Yoon Lee

Dae Hyun Kim

Sung-Rea Kim

A 3D nanopore device for characterizing biopolymer molecules includes a first selecting layer having a first axis of selection. The device also includes a second selecting layer disposed adjacent the first selecting layer and having a second axis of selection orthogonal to the first axis of selection. The device further includes an third electrode layer disposed adjacent the second selecting layer, such that the first selecting layer, the second selecting layer, and the third electrode layer form a stack of layers along a Z axis and define a plurality of nanopore pillars.

Nanopore device and method of manufacturing same

A method of manufacturing and using a nanofluidic NAND transistor sensor array scheme including a plurality of nanopore channel pillars, a plurality of respective fluidic channels, a plurality of gate electrodes, a top chamber, and a bottom chamber includes placing a sensor substrate in an electrolyte solution comprising biomolecules and DNA. The method also includes placing first and second electrodes in the electrolyte solution (Vpp and Vss of the nanofluidic NAND transistor); forming the nanopore channel pillars; placing the gate electrodes and gate insulators in respective walls of the nanopore channel pillars; applying an electrophoretic bias in the first and second electrodes; applying a bias in the gate electrodes; detecting a change in an electrode current in the electrolyte solution caused by a change in a gate voltage; and detecting a change in a surface charge in nanopore channel electrodes in the respective fluidic channels.

Nanopore device and methods of electrical array addressing and sensing

A method of synthesizing an oligonucleotide using a nanofluidic device including a plurality of nanopore channels, a plurality of electrodes, and an electrolyte solution, includes coupling a primer to an inner wall of a nanopore channel of the plurality of nanopore channels, the primer having a protecting group. The method also includes applying a voltage to an electrode of the plurality of electrodes that corresponds to the nanopore channel to produce an acid from the electrolyte solution at the electrode. The electrode includes an anode and a cathode disposed at opposite sides of the nanopore channel. The method further includes the acid removing the protecting group from the primer. Moreover, the method includes coupling a nucleotide to the primer with the protecting group removed to form an intermediate product. In addition, the method includes repeating the steps on the intermediate product until the oligonucleotide is synthesized.

Nanopore device and methods of biosynthesis using same

A method of calibrating a nanofluidic device including a plurality of nanopore channels, a plurality of gating nanoelectrodes, and a plurality of sensing nanoelectrodes, includes applying a selecting voltage across a gating nanoelectrode of the plurality of gating nanoelectrodes to select a nanopore channel. The method also includes tuning the nanopore channel by applying a first biasing voltage across a sensing electrode of the plurality of sensing nanoelectrodes, and receiving a plurality of currents over a plurality of frequencies. The method further includes generating a calibration data set from the pluralities of frequencies and currents. Moreover, the method includes comparing the calibration data set with a reference data set. In addition, the method includes when the calibration data set differs from the reference data set by more than a predetermined threshold, repeating the method with a second biasing voltage different from the first biasing voltage.

Nanopore device and methods of detecting and classifying charged particles using same

A method for programming a flash memory cell comprises providing input data to the flash cell and providing a segmented programming pulse to the flash memory cell. The segmented programming pulse includes programming segments, each successive programming segment including a programming potential higher than the programming potential used in a previous programming segment, each programming segment followed by a zero-potential compare segment. The output of the flash memory cell is compared with the input data during the compare segment after each programming segment. The segmented programming pulse is terminated if the output of the flash memory cell matches the input data. The programming potential in each programming segment is increased during the programming segment. The programming potential in successive segments is either is increased or stepped up to the final value of the previous programming segment.

Programming method for non-volatile memory and non-volatile memory-based programmable logic device

A multiple memory layer device has a plurality of stacked memory layers. Each of the memory layers has: a charge generating layer of p-type semiconductor material with a plurality of n-type diffusion regions; an insulating layer disposed over the charge generating layer; a charge storing layer disposed over the insulating layer; and another insulating layer disposed over the charge storing layer. A gate is disposed over the top insulting layer in the uppermost memory layer in the plurality of stacked memory layers.

Memory device with multiple memory layers of local charge storage

A method for providing redundancy in a floating charge trap device based programmable logic device includes the steps of sensing for a predetermined amount of stored charge in a first area of a floating trap devices in a floating trap device pair, and sensing for the predetermined amount of stored charge in a second area of the floating trap devices in the floating trap device pair when the charge in the stored charge in the first area in one of the floating trap devices is below the predetermined amount.

Methods of redundancy in a floating trap memory element based field programmable gate array

The problem of bit disturb is reduced by discharging the floating bit lines of a nonvolatile memory array during programming. An illustrative virtual ground memory array uses single transistor floating gate type memory cells that are programmed using Fowler-Nordheim ('FN') tunneling, highly conductive and lengthy bit lines, buried and relatively short sub-bit lines and a programming discharge circuit for controlling spurious voltages on the bit lines that can arise when some of the bit lines are left floating during programming. Discharge control transistor respectively coupled to the bit lines direct current into a discharge section. A discharge section may be provided for each bit line, or shared by all bit lines. The discharge section may be a fixed circuit section for use through the programming process or may be selected from multiple discharge options.

Nonvolatile memory having bit line discharge, and method of operation thereof

An asymmetrical virtual ground single transistor floating gate memory cell has a floating gate that overlies a channel region in a p-well, the channel region lying between a heavily doped n+ drain region and a lightly doped n&#x2212; source region. A heavily doped p+ region known as a 'halo' is disposed in the channel adjacent the heavily doped n+ drain. The floating gate is spaced away from the channel region by a generally thin tunnel oxide. A lightly doped source with a graded source/channel junction reduces source side CHE generation. In one variation, a thicker oxide between the source and the floating gate reduces CHE injection from the source side. A heavily doped drain with a halo implant in the channel adjacent the drain enhances drain side CHE generation.

Virtual ground single transistor memory cell, memory array incorporating same, and method of operation thereof

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Palo Alto, CA, United States of America

Kyung Joon Han