Samsung Electronics Co., Ltd.

Lg Chem, Ltd

Kyung-Hyun Kim

Yong-Sun Ko

Byoung-Moon Yoon

Jong-Heun Lim

Sang-rok Hah

Chang-ki Hong

Tae-Hyun Kim

Chung-Ki Min

Jae-Phil Boo

Hyo-Jung Kim

Jeong-Lim Nam

Ki-Jong Park

Jin-I Lee

Ki-Ho Bae

Yong-Hoon Son

Phil-Ouk Nam

Yeon-Sil Sohn

Won-Bong Jung

Kwang-Bok Kim

Bo-un Yoon

Ji-hong Kim

Hyo-Jin Lee

Han-Mei Choi

Won-Jun Lee

Tae-Won Kim

Suk-Hun Choi

Kwang-bok Kim

Chang-Ki Hong

Jong-won Lee

Jae-Jin Shin

Chang-Sup Mun

Young-rae Park

Jung-Yup Kim

Young-Suk Kim

Kwang-Chul Park

In-jun Yeo

Byoung-moon Yoon

Hyun-ho Jo

Myung-Jung Pyo

In-Kwon Kim

Byeong-Ju Kim

Seong-Yong Ahn

Jong-Hun Cho

Chang-Ryang Jang

Kohji Kanamori

Cheol-Woo Park

Ki-Hyun Hwang

Jae-Hwang Sim

Sung-Jun Kim

Young-Woo Park

Chang-seok Kang

Jae-Duk Lee

Dong-Keun Kim

Bum-Soo Kim

Seung-Pil Chung

Jae-Dong Lee

Yoo-Cheol Shin

Dong-jun Kim

Jung-Geun Jee

U-in Chung

Min-Soo Cho

Dong-Chul Yoo

Kwang-Wook Lee

Hong-Seong Son

Kyung-tae Nam

Jae-woong Lee

In-Seak Hwang

Yong-Tak Lee

Jong-won Kim

Chan-Jin Park

Dae-Hyuk Chung

Jae-Kwang Choi

Eui-Youl Ryu

Jun-ho Jeong

In-joon Yeo

Yi-Koan Hong

Chang-Hyeon Nam

Cha-Dong Yeo

Ja-hyung Han

Young-Hee Kim

Dong-keun Kim

Yongsam Moon

Soo-Young Tak

Hyun-Ho Cho

Ji-Woon Im

Kwang Chul Park

Choong-Kee Seong

Yu-Na Kim

Dae-hong Eom

Yeol Jon

Myoung-Sik Han

Chan-wook Seo

Young-beom Pyon

Hyun-Min Park

Chang-Lyong Song

Myung-sik Han

In-Jun Yeo

Dai-Goun Kim

Kyu-Chan Park

Sun-wung Lee

A chemical mechanical polishing machine includes a polishing head assembly including a polishing head body and a membrane disposed at a bottom of the polishing head body. The bottom surface of the membrane includes a hydrophobic area and a hydrophilic area.

Chemical mechanical polishing machine and polishing head assembly

A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a vertical direction with respect to a top surface of the substrate, a plurality of non-metal gate patterns surrounding the channels and being stacked on top of each other and spaced apart from each other along the vertical direction, and a plurality of metal gate patterns stacked on top of each other. The metal gate patterns are spaced apart from each other along the vertical direction. Each of the metal gate patterns surrounds a corresponding one of the non-metal gate patterns.

Vertical memory devices and methods of manufacturing the same

A vertical memory device includes a substrate, a channel on the substrate, extending in a vertical direction with respect to a top surface of the substrate, and including a protrusion at a lower portion of the channel, the protrusion extending in a parallel direction with respect to the top surface of the substrate, a semiconductor pattern connecting the protrusion and the substrate, and gate lines stacked and spaced apart from each other in the vertical direction, the gate lines on the protrusion and the semiconductor pattern and surrounding the channel.

Vertical memory devices

A nonvolatile memory device includes a conductive line disposed on a substrate and vertically extended from the substrate, a first channel layer disposed on the substrate and vertically extended from the substrate, wherein the first channel layer is spaced apart from the conductive line, a second channel layer vertically extended from the substrate, wherein the second channel layer is disposed between the first channel layer and the conductive line, a first gate electrode disposed between the conductive line and the second channel layer, wherein the first gate electrode includes a first portion having a first thickness and a second portion having a second thickness that is different from the first thickness, and a second gate electrode disposed between the first channel layer and the second channel layer, wherein the second gate electrode has the second thickness.

Nonvolatile memory device and a method for fabricating the same

A preliminary tunnel insulation pattern and a preliminary charge storage pattern are formed on each active pattern extending in a direction, and a trench is defined between structures including the active pattern, the preliminary tunnel insulation pattern and the preliminary charge storage pattern. A preliminary isolation pattern partially fills the trench. A dielectric layer and a control gate electrode layer are formed on the preliminary charge storage pattern and the preliminary isolation pattern. The control gate electrode layer, the dielectric layer, the preliminary charge storage pattern and the preliminary tunnel insulation pattern are patterned to form gate structures including a tunnel insulation pattern, a charge storage pattern, a dielectric layer pattern and a control gate electrode. The preliminary isolation pattern is isotropically etched to form an isolation pattern and a first air gap. An insulating interlayer is formed between the gate structures to keep the first air gap.

Non-volatile memory device and method of manufacturing the same

A nonvolatile memory device including a substrate which includes a cell array region and a connection region, an electrode structure formed on the cell array region and the connection region and including a plurality of laminated electrodes, a first recess formed in the electrode structure on the connection region and disposed between the cell array region and a second recess formed in the electrode structure on the connection region, and a plurality of vertical wirings formed on the plurality of electrodes exposed by the first recess.

The present invention relates to a method of preparing a vinyl chloride polymer, and more precisely, a method of preparing a vinyl chloride polymer having excellent processability by raising a final polymerization temperature up to 5&#x2dc;20&#xb0; C. from an first polymerization temperature.

Method of preparing vinyl chloride polymers having superior processability

The present invention provides a method of preparing vinyl chloride polymer having excellent processability and high bulk density by the separate stepwise additions of vinyl chloride monomer during suspension polymerization.

Method for production of vinyl chloride-based polymer by suspension polymerization

According to example embodiments of inventive concepts, a non-volatile memory device includes a substrate including a second impurity region crossing a first impurity region, and channel regions extending in a vertical direction on the substrate. Gate electrodes may be separated from each other in a vertical direction and a horizontal direction along outer walls of the channel regions. A first insulating interlayer may be on the gate electrodes and the channel regions, where the first insulating interlayer defines a contact hole between at least one adjacent pair gate electrodes and a contact plug is formed in the contact hole to be electrically connected to the second impurity region. An etch stop layer pattern may be on the contact plug and the first insulating interlayer.

Non-volatile memory device including etch stop layer pattern

Methods of manufacturing semiconductor devices include forming an integrated structure and a first stopping layer pattern in a first region. A first insulating interlayer and a second stopping layer are formed. A second preliminary insulating interlayer is formed by partially etching the second stopping layer and the first insulating interlayer in the first region. A first polishing is performed to remove a protruding portion. A second polishing is performed to expose the first and second stopping layer patterns.

Methods of manufacturing semiconductor devices

A first insulating interlayer is formed on a substrate including first and second regions. The first insulating interlayer has top surface, a height of which is greater in the first region than in the second region. A first planarization stop layer and a second insulating interlayer are formed. The second insulating interlayer is planarized until the first planarization stop layer is exposed. The first planarization stop layer and the first and second insulating interlayers in the second region are removed to expose the substrate. A lower mold structure including first insulation layer patterns, first sacrificial layer patterns and a second planarization stop layer pattern is formed. The first insulation layer patterns and the first sacrificial layer patterns are alternately and repeatedly formed on the substrate, and a second planarization stop layer pattern is formed on the first insulation layer pattern.

Multiple mold structure methods of manufacturing vertical memory devices

In an embodiment, a chemical mechanical polishing method for a substrate having a first layer and a stepped portion. A surface of the first layer is positioned above an upper face of the stepped portion. A polishing process for selectively removing the stepped portion is performed on the first layer by using a first slurry composition that has a self-stopping characteristic so that the first layer is changed into a second layer having a substantially flat surface. A second polishing process is performed using a second slurry composition that does not have the self-stopping characteristic, until the upper face of the stepped portion is exposed.

Chemical mechanical polishing method

A capacitor includes an object or a substrate including an insulation layer having an opening, an electrode structure having conductive patterns, a dielectric layer and an upper electrode. The electrode structure may have a first conductive pattern including metal and a second conductive pattern including metal oxide generated from the first conductive pattern. The first conductive pattern may fill the opening and may protrude over the insulation layer. The second conductive pattern may extend from the first conductive pattern. The electrode structure may additionally include a third conductive pattern disposed on the second conductive pattern. The capacitor including the electrode structure may ensure improved structural stability and electrical characteristics.

Capacitor having an electrode structure, method of manufacturing a capacitor having an electrode structure and semiconductor device having an electrode structure

A semiconductor device includes an interlayer insulating layer disposed on a substrate, the interlayer insulating layer comprising an opening exposing the substrate, a barrier layer pattern disposed within the opening, and a conductive pattern disposed on the barrier layer pattern, the conductive pattern having an oxidized portion extending out of the opening and a non-oxidized portion within the opening, wherein a width of the conductive pattern is determined by a thickness of the barrier layer pattern.

Semiconductor device having a conductive structure including oxide and non oxide portions

Growing community of inventors

Seoul, South Korea

Kyung-Hyun Kim