Skhynix Inc.

Goldstar, Co., Ltd.

Samsung Sds Co., Ltd.

Riiid Inc.

Neo Sastech Co., Ltd.

Ebay, Incorporated

Industry-university Cooperation Foundation Hanyang University

Posco

Naver Corporation

Genoray Co., Ltd.

Kyung Hoon Kim

Jung Cheol Kim

Oh H Kwon

Kyung Seop Hong

Dong Y Oh

Gyu S Choe

Dong S Gil

Ha I Lee

Byoung H Kwon

Kyeong B Park

Joo Hee Lee

Ji Hyo Kang

Yong Jin

Seung Won Choi

Myeong Jae Park

Woo Yeol Shin

Dong Hyun Kuem

Hyun Soo Park

Soon Woo Kwon

Ji Hwan Park

Gi Moon Hong

Gang Sik Lee

Jae We Heo

Ha Jun Jeong

Joo Hyung Chae

Han Kyu Chi

Jae Hoon Cha

Sang Yeon Byeon

Jae Hyeok Yang

Jin Seo Yoon

Byeong Cheon Jeong

Hyun Jung Park

Min Sung Noh

Min Gyu Maing

Se Ra Jeong

Sun Ki Cho

Dong Won Lee

Hong Bae Kim

Choong Hee Lee

Hyun Wook Yang

Nam Young Ahn

Kyu Young Kim

In Sik Yoon

Dae Seong Kim

Yung Seong Lee

Jee Yeon Keh

Jin-Hwan Jun

Jung Il Ahn

Hye Jin Kang

Heung Seop Ahn

Woo Je Kim

Hong Chul Lee

Un Jee Park

Keon Su Lee

Il Gu Lee

Yeon Seok Song

Hyoung Min Cho

Joo Hwan Lee

Seon H Kim

Dal W Kim

Sun Wook Lee

A command address control circuit includes a command decoding circuit, an error decision circuit, and a shifting circuit. The command decoding circuit detects a type of command address signal set in synchronization with a reference clock signal. The error decision circuit detects whether an error is present in the command address signal set, and generates a block signal based on the type of command address signal set and the results of the detection of an error. The shifting circuit outputs the command address signal set as an internal command address signal set based on the reference clock signal and the block signal.

Command address control circuit, and semiconductor apparatus and semiconductor system including the command address control circuit

A semiconductor apparatus includes a command address control circuit. The command address control circuit is configured to receive a row command address signal and a column command address signal, and is configured to selectively invert the row command address signal and the column command address signal based on a logic level of at least one bit of the row command address signal.

Command address control circuit and semiconductor apparatus and semiconductor system including the command address control circuit and semiconductor apparatus

A clock distribution network includes a global clock tree and a local clock tree. When the clock distribution network is activated, the local clock tree is first activated, and the voltage levels of first and second output clock signals are set as a common mode voltage level. When the global clock tree is activated, the global clock tree generates first and second global clock signals from first and second input clock signals. The local clock tree generates the first and second output clock signals from the first and second global clock signals.

Clock distribution network, semiconductor device and semiconductor system including the same, and clock distribution method thereof

A clock distribution circuit includes a global distribution circuit, a first local distribution circuit and a second local distribution circuit. The global distribution circuit receives external clock signals and generates internal clock signals and primary reference clock signal set according to the external clock signals. The first local distribution circuit receives the internal clock signals and the primary reference clock signal set and generates a secondary reference clock signal set according to the internal clock signals and the primary reference clock signal set. The second local distribution circuit receives the internal clock signals and the secondary reference clock signal set and generates a thirdly reference clock signal set according to the internal clock signals and the secondary reference clock signal set.

Clock distribution circuit and semiconductor apparatus including the same preliminary class

A semiconductor apparatus includes a clock distribution network, a data output circuit, and a data input circuit. The clock distribution network receives a system clock signal and drives the system clock signal to a CMOS level and a CML level to signal in different manners. The data output circuit outputs data based on the clock signal driven to the CMOS level. The data input circuit receives data based on the clock signal driven to the CML level.

Semiconductor apparatus performing a plurality of clock signaling operations and semiconductor system including the same

The present invention relates to a method for displaying learning content of a terminal and an application program therefor. The method for displaying learning content of a terminal of the present invention comprises the steps of: displaying text with a group of questions on a first layer; displaying a first question card corresponding to a first question on a second layer; and when a continuous touch gesture in a touch input is received in the second layer, displaying, on the second layer, a second question card corresponding to a second question according to the touch gesture, wherein the question card includes one or more examples that are selectable by a learner. According to the present invention, it is possible to effectively display learning content including a large amount of information such as multiple choice questions on a limited size screen.

Method for displaying learning content of terminal and application program therefor

Devices for reducing power consumption and skew for transmission of signals in a clock distribution circuit are described. A global distribution circuit is configured to divide external clock signals to generate first divided multiphase clock signals and divide one of the first divided multiphase clock signals to generate a reference clock signal. A local distribution circuit is configured to generate second divided multiphase clock signals according to a portion of the first divided multiphase clock signals and the reference clock signal.

Clock distribution circuit and semiconductor apparatus including the same

A semiconductor system includes a slave including a plurality of unit memory regions. The semiconductor system further includes a master configured to perform a training operation by writing test data to the plurality of unit memory regions, reading the written test data, and determining a pass/fail result for the read test data.

Semiconductor apparatus and semiconductor system with training function

Methods, systems, and computer storage media are provided for presenting a preview of a customized landing page at a search engine are provided. The search engine may provide search results that comprise a preview of the customized landing page, where a user may interact with the customized landing page while at the search engine. The user may select a landing-page link provided by the customized landing page using the preview at the search engine. Based on selecting the landing-page link, the user is navigated directly from the search engine to a webpage associated with the landing-page link. A customized landing page may be generated for display at the preview of the search engine, where the customized landing page includes a user-specific element, such as information specific to the user, which may be based on a user identifier communicated from the search engine to a customizable landing-page website.

Presenting a customized landing page as a preview at a search engine

A semiconductor apparatus includes first transmitters allocated to a first data byte, and second transmitters allocated to a second data byte, wherein a power supply node of each transmitter allocated to a deactivated byte of the first data byte and the second data byte is coupled with a ground terminal.

Semiconductor apparatus

A semiconductor apparatus includes an input selection circuit that selects one of a first input signal and a second input signal in response to a control signal, and outputs the selected input signal as a selection signal, wherein swing levels of the first input signal and the second input signal are different one another. The semiconductor apparatus also includes a conversion circuit that generates an output signal, in response to the selection signal, which swings to a level substantially identical to a level of the second input signal.

Semiconductor apparatus using swing level conversion circuit

A method and a terminal device for executing a radio application are disclosed. The method for executing a radio application comprises the steps of: allowing a radio virtual machine (RVM) of a reconfigurable mobile device to reference a radio programming interface (RPI); and replacing at least one abstract processing element (APE) of the RVM with at least one elementary RVM according to an RVM hierarchical structure referenced by the RPI.

Method and terminal device for executing radio application

A memory module includes a module substrate. The module substrate includes a plurality of regions, on which a plurality of memory apparatuses are mounted. A plurality of inductors are formed in the plurality of regions of the memory module substrate, respectively.

Memory apparatus and memory module including a power management integrated circuit

A semiconductor memory apparatus may include a first memory apparatus and a second memory apparatus, and may perform various operation modes. The first and second memory apparatuses may independently perform a write operation and a read operation in a first operation mode. The first memory apparatus may perform a write operation and a read operation and the second memory apparatus may perform a write operation in a second operation mode. The second memory apparatus may perform a write operation and a read operation in a third operation mode.

Semiconductor memory apparatus relating to various operation modes, and memory module and system including the same

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Seoul, South Korea

Kyung Hoon Kim