Hynix Semiconductor Inc.

Skhynix Inc.

Ipopcorn Co., Ltd.

Kt Corporation

Hynis Semiconductor Inc.

Kyung-Hoon Kim

Taek-Sang Song

Dae-Han Kwon

Chang-Kyu Choi

Dae-Kun Yoon

Sang-Sic Yoon

Yong-Ki Kim

Sang-Yeon Byeon

Patrick B Moran

Jun-Woo Lee

Myeong-Jae Park

Han-Kyu Chi

Bo-Kyeom Kim

Kyung-Whan Kim

Sung-Eun Lee

Hyun-Min Lee

Jae-Joon Choi

Tae-Heui Kwon

Woo-Yeol Shin

Ju-No Yoon

Yong-Ju Kim

Kyu-Young Kim

Dong-Keun Kim

Sung-Ho Hwang

Sang-Sik Yoon

Sang-Man Bak

Tae-Wook Kang

Jong-Ho Kang

Myoung-Gyu Son

Hong-Bae Kim

The present invention relates to a technology for providing a place/time-based local interactive service, which provides multi-formatted content information to a user moving while carrying a smart terminal having a dedicated application installed therein. In particular, when moving into a place where a specific wired/wireless AP is installed, a user who carries a smart terminal with a dedicated application activated therein can receive multi-formatted content information previously mapped with the place using a place/time, without a separate manipulation of the smart terminal. According to the present invention, time periods during which the user carrying the smart terminal stays at the place where the specific wired/wireless AP is installed are accumulated and managed using time coins, and the user is then given a benefit according to the accumulated time periods.

Sound signal-based local interactive platform system and local interactive service providing method using same

A clock data recovery circuit may include: a phase comparison unit suitable for comparing input data with a phase of a multi-phase clock, and for generating an up/down signal corresponding to the comparison result; a filtering unit suitable for counting the up/down signal based on an upper threshold value and a lower threshold value, for setting, when an overflow occurs, the lower threshold value to an initial value for the count of the up/down signal, or when a underflow occurs, the upper threshold value to the initial value for the count of the up/down signal, and for generating a control code corresponding to one of the underflow and the overflow; and a phase rotating unit suitable for adjusting the phase of the multi-phase clock in response to the control code outputted from the filtering unit.

Clock data recovery circuit, integrated circuit including the same, and clock data recovery method

The present invention relates to a technology for providing a place/time-based local interactive service, which provides multi-formatted content information to a user moving while carrying a smart terminal having a dedicated application installed therein. In particular, when moving into a place were a specific wired/wireless AP is installed, a user who carries a smart terminal with a dedicated application activated therein can receive multi-formatted content information previously mapped with the place using a place/time, without a separate manipulation of the smart terminal. According to the present invention, time periods during which the user carrying the smart terminal stays at the place where the specific wired/wireless AP is installed are accumulated and managed using time coins, and the user is then given a benefit according to the accumulated time periods.

An integrated circuit may include: a phase detector suitable for generating a delay control signal by comparing the phases of first and second clock signals to first and second target positions, a variable delay unit suitable for shifting the first and second clock signals to the first and second target positions, respectively, in response to the delay control signal, and a position controller suitable for varying the first and second target positions according to an operation mode.

Integrated circuit

A delay circuit includes: a plurality of delay units that are serially coupled with each other in a form of loop and sequentially delay an input signal of the delay circuit; an input control unit that selects a delay unit to receive the input signal of the delay circuit among the plurality of the delay units; and an output control unit that controls an output signal of a predetermined delay unit among the plurality of the delay units to be outputted as an output signal of the delay circuit, when the output signal of the predetermined delay unit is enabled N times, where N is an integer equal to or greater than 0.

Delay circuit

An integrated circuit includes a variable resistance unit including at least one transistor that receives a control signal and changes a resistance through the transistor in response to the control signal in a programming operation mode and an information detection unit configured to detect programming information in response to an output voltage of the variable resistance unit in a normal operation mode.

Integrated circuit for storing information

A semiconductor memory device has a duty cycle correction circuit capable of outputting a duty cycle corrected clock and its inverted clock having substantially exactly 180&#xb0; phase difference therebetween. The semiconductor memory device includes a duty cycle corrector configured to receive a first clock and a second clock to generate a first output clock and a second output clock whose duty cycle ratios are corrected in response to correction signals, and a clock edge detector configured to generate the correction signals corresponding to an interval between a reference transition timing of the first output clock and a reference transition timing of the second output clock.

Semiconductor memory device and method for driving the same

A method for converting a SMS sent through a mobile communication network into a SMS or MMS in a previously registered format includes the steps of: receiving a SMS from a certain sending subscriber, determining whether the corresponding sending subscriber is subscribed to a SMS converting service, then converting the SMS into a previously registered format in case the sending subscriber is subscribed to the SMS converting service, and then sending the converted message to a designated receiving terminal.

System and method for decorating short message from origination point

A latency control circuit includes a delay unit configured to delay an input signal for a delay corresponding to a phase difference between an external clock and an internal clock and generate a delayed input signal, a delay information generation unit configured to generate a delay information based on a latency information and a delay amount of the input signal caused by a chip including the latency control circuit, a shift unit configured to shift the delayed input signal for a time period corresponding to the delay information in synchronism with the internal clock and an asynchronous control unit configured to selectively control the shift unit to output the delayed input signal without performing a shift operation.

Latency control circuit and semiconductor memory device including the same

A semiconductor memory device capable of measuring a temperature without the influence of noise includes a temperature sensing device for sensing a current temperature in response to a control signal, wherein the semiconductor memory device enters a power save mode for a predetermined time starting from an activation of the control signal and wherein the power save mode has substantially no power consumption. A method for driving a semiconductor memory device in accordance with the present invention includes sensing a current temperature in response to a control signal and entering a power save mode for a predetermined time starting from an activation of the control signal, wherein the power save mode has substantially no power consumption.

Semiconductor memory device with temperature sensing device capable of minimizing power consumption in refresh

A clock data recovery (CDR) circuit occupies a small area required in a high-integration semiconductor device, electronic device and system and is easy in design modification. The CDR circuit includes a digital filter configured to filter phase comparison result signals received during predetermined periods and output control signals, a driver configured to control the digital filter by adjusting the predetermined periods, and an input/output circuit configured to recognize an input and output of data and clock in response to the control signals.

Clock data recovery circuit and method for operating the same

A semiconductor memory device can optimize the layout area and current consumption based on multi-phase clock signals which are generated by dividing a source clock signal using a reset signal without a delay locked loop and a phase locked loop in order to have various phase information of low frequencies and different activation timings with a constant phase difference.

Semiconductor device and operation method thereof for generating phase clock signals

An output circuit of a semiconductor device includes a signal selector configured to receive first and second input data signals and sequentially outputting the first and second input data signals in response to a phase signal; and an output level controller configured to control a voltage level of an output signal of the signal selector based on the first and second input data signals.

Output circuit of semiconductor device

Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus includes a plurality of signal receiving units configured to receive signals through a plurality of input/output pads and transfer the signals according to a receiving reference clock, the signal receiving units being divided into groups, a plurality of phase detection units configured to detect phases of signals output from the groups of the signal receiving units, a plurality of phase detection control units configured to control the phase detection units so that the phase detection units sequentially detect the phases of the signals output from each of the groups of the signal receiving units and a notification unit configured to output signals output from the phase detection units.

Growing community of inventors

Kyoungki-do, South Korea

Kyung-Hoon Kim