Samsung Electronics Co., Ltd.

Kyung-ah Jeong

Sun-young Shin

Jin-hong Oh

Jong-ho Roh

Min-Je Jun

Yong-Kwon Cho

Gahng-Soo Moon

Won-Joon Jang

A system on a chip may include a codec module configured to receive an image including a plurality of first pixel data and output a plurality of second pixel data through a system bus. The codec module comprises at least one (M+N) bit logic circuit including M bit logic and N bit logic. The codec module is configured to operate in a first mode where the (M+N) bit logic circuit performs a dithering operation on the first pixel data of (M+N) bits and generates the second pixel data including at least M bits. The codec module is configured to operate in a second mode where the M-bit logic selectively operates and outputs the second pixel data of M bits.

Image processing device, image processing system including image processing device, system-on-chip including image processing system, and method of operating image processing system

An image processing system comprises a first image processing device configured to process a frame of image data comprising a plurality of pixels, each having corresponding pixel values. Each of the pixel values include a first and second set of bits that may be separately or simultaneously accessed and/or processed. The first set of bits may correspond to the more significant bits of each pixel and the second set of bits may correspond to the less significant bits. In some examples the number of bits in each of the first and second set of bits may correspond to the width of a used data bus and/or features of a peripheral device connected to the image processor, such as a display.

Image processor, image processing system including image processor, system-on-chip including image processing system, and method of operating image processing system

A method of processing image data comprises processing a frame of image data comprising a plurality of pixels, each having corresponding pixel values. Each of the pixel values include a first and second set of bits that may be separately or simultaneously accessed and/or processed. The first set of bits may correspond to the more significant bits of each pixel and the second set of bits may correspond to the less significant bits. In some examples the number of bits in each of the first and second set of bits may correspond to the width of a used data bus and/or features of a peripheral device connected to the image processor, such as a display.

A wireless display subsystem includes a hardware composition generator, a hardware video encoder, and a wireless hardware transport stream multiplexer. The hardware composition generator reads video data from a memory device and generates video frame data by synthesizing the video data. The hardware video encoder receives the video frame data in an on-the-fly (OTF) manner from the hardware composition generator and generates a video stream by encoding the video frame data. The wireless hardware transport stream multiplexer receives the video stream in the OTF manner from the hardware video encoder, reads an audio stream from the memory device, multiplexes the video stream and the audio stream, and generates a wireless display packet by packetizing the multiplexed video and audio streams.

Wireless display subsystem and system-on-chip

An image processor processes a plurality of pixels. Each of the pixels include a first and second set of bits that can be separately or simultaneously in first and second regions of a memory using one or more addresses. The first set of bits may correspond to the more significant bits of each pixel and the second set of bits may correspond to the less significant bits. In some examples the number of bits in each of the first and second set of bits may be selected according to the width of a used data bus and/or features of a peripheral device connected to the image processor such as a display.

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Seoul, South Korea

Kyung-ah Jeong