Advanced Semiconductor Engineering, Inc.

Motorola Corporation

Kyujin Jung

Kun-A Kang

Hyung Jun Park

Bishnu Prasanna Gogoi

David Joseph Monk

Theresa A Maudie

Dave S Mahadevan

Jun Hong Lee

Gordon D Bitko

Song Woon Kim

Bill McDonald

A low-pin-count chip package including a die pad for receiving a semiconductor chip and a plurality of connection pads electrically coupled to the semiconductor chip. The semiconductor chip, the die pad, and the connection pads are encapsulated in a package body such that the lower surfaces of the die pad and the connection pads are exposed through the package body. The present invention is characterized in that the die pad and the connection pads have a substantially concave profile thereby prolonging the time for moisture diffusion into the package as well as enhancing the 'locking' of the die pad and the connection pads in the package body. The present invention further provides a method of producing the low-pin-count chip package described above.

Low-pin-count chip package and manufacturing method thereof

A low-pin-count chip package including a die pad for receiving a semiconductor chip and a plurality of connection pads electrically coupled to the semiconductor chip. The semiconductor chip, the die pad, and the connection pads are encapsulated in a package body such that the lower surfaces of the die pad and the connection pads are exposed through the package body. The present invention is characterized in that the die pad and the connection pads are formed by etching such that they have a concave profile and a thickness far larger than that of conventional die pad and connection pads formed by plating. This prolongs the path and time for moisture diffusion into the package, and significantly increases the area of the interface between the package body and the die pad as well as the connection pads thereby promoting adhesion therebetween. The present invention further provides a method of producing the low-pin-count chip package described above.

A low-pin-count chip package including a die pad for receiving a semiconductor chip and a plurality of connection pads electrically coupled to the semiconductor chip. The semiconductor chip, the die pad, and the connection pads are encapsulated by a package body in a manner that the lower surfaces of the die pad and the connection pads are exposed through the package body. The present invention is characterized in that the die pad and the connection pads have a T-shaped profile thereby prolonging the time for moisture diffusion into the package as well as enhancing the &ldquo;locking&rdquo; of the die pad and the connection pads in the package body. The present invention further provides a method of producing the low-pin-count chip package described above.

Selective encapsulation of a micro electro-mechanical pressure sensor provides for protection of the wire bands ( ) through encapsulation while permitting the pressure sensor diaphragm ( ) to be exposed to ambient pressure without encumbrance or obstruction. Selective encapsulation is made possible by the construction of a protective dam ( ) around the outer perimeter of a pressure sensor diaphragm ( ) to form a wire bond cavity region between the protective dam ( ) and the device housing ( ). The wire bond cavity may be encapsulated with an encapsulation gel ( ) or by a vent cap ( ). Alternatively, the protective dam ( ) may be formed by a glass frit pattern ( ) bonding a cap wafer ( ) to a device wafer ( ) and then dicing the two-wafer combination into individual dies with protective dams attached.

Micro electro-mechanical system sensor with selective encapsulation and method therefor

A low-pin-count chip package including a die pad for receiving a semiconductor chip and a plurality of connection pads electrically coupled to the semiconductor chip. The semiconductor chip, the die pad, and the connection pads are encapsulated in a package body such that the lower surfaces of the die pad and the connection pads are exposed through the package body. The present invention is characterized in that the die pad and the connection pads have a substantially concave profile thereby prolonging the time for moisture diffusion into the package as well as enhancing the &ldquo;locking&rdquo; of the die pad and the connection pads in the package body. The present invention further provides a method of producing the low-pin-count chip package described above.

A method for packaging a semiconductor chip, generally comprising the following steps of: (a) forming a plurality of openings on the top surface of the conducting substrate, wherein the upper portions of the openings are formed larger than the lower portions of the openings; (b) forming insulating sections in the conducting substrate by filling an insulating material in the openings; (c) forming a plurality of leads insulated by the insulating sections by planarizing the bottom surface of the conducting substrate to expose and form planarized bottom surfaces of the insulating sections; (d) mounting a semiconductor chip on the bottom surface of the conducting substrate; (e) providing a plurality of conducting wires to electrically connect the semiconductor chip to the leads; and (f) encapsulating the semiconductor chip and the conducting wires. The package according to the present invention is characterized by upper portions of the leads that are purposedly formed larger than lower portions of the leads which prevents the leads from being easily detachable and the package from being destructed by water, the reliability of the package is thus increased.

Growing community of inventors

Kyunggi-do, South Korea

Kyujin Jung