Samsung Electronics Co., Ltd.

Snur & Db Foundation

Global Frontier Center-multiscale Energy Systems

Global Frontier Center for Multiscale Energy System

Kyuhee Han

Jongmin Baek

Hoseop Choi

Woojin Lee

Sanghoon Ahn

Wookyung You

Sang Ki Nam

Man Soo Choi

Deokyoung Jung

Sunggil Kang

Kwangyoub Heo

Yeongkwang Lee

Kinam Jung

Kyungyeon Ha

Jiyoung Kim

Naein Lee

Byunghee Kim

Sangki Nam

Changsoon Kim

Jangho Lee

Dongkyu Shin

Kyeongbeom Park

Akira Koshiishi

Suhyun Park

Taejin Yim

Sangshin Jang

Soonam Park

Beomjin Yoo

Minhyoung Kim

Yeonggil Kim

Seonghun Lim

Dongjoon Lee

Sukbyung Chae

Hyungchae Kim

Jongcheon Lee

Hyangki Sung

Sungbin Park

Namjin Cho

Yeontae Kim

Keesoo Park

Eunsok Choi

Wonhyuk Jang

Jeongmin Bang

An integrated circuit device according to the inventive concepts includes lower wiring structures formed on a substrate, an air gap arranged between the lower wiring structures, a capping layer covering an upper surface of the air gap, an etch stop layer conformally covering an upper surfaces of the lower wiring structures and the capping layer and having a protrusion and recess structure, an insulating layer covering the etch stop layer, and an upper wiring structure penetrating the insulating layer and connected to the upper surface of the lower wiring structure not covered with the etch stop layer, wherein the upper wiring structure covers a portion of an upper surface of the capping layer, and a level of the upper surface of the capping layer is higher than a level of the upper surface of the lower wiring structures.

Integrated circuit device including air gaps and method of manufacturing the same

A semiconductor device includes a first insulating layer disposed on a substrate, a first wiring disposed in the first insulating layer, a first insulating barrier layer disposed on the first insulating layer, an etch-stop layer disposed on the first insulating barrier layer and having an area smaller than an area of the first insulating barrier layer in a plan view, a resistive metal pattern disposed on the etch-stop layer, a second insulating barrier layer disposed on the resistive metal pattern, a second insulating layer covering the first and second insulating barrier layers, a second wiring disposed in the second insulating layer, and a first conductive via disposed between the resistive metal pattern and the second wiring to penetrate through the second insulating barrier layer and the second insulating layer and electrically connect the resistive metal pattern and the second wiring.

Semiconductor device and method of manufacturing semiconductor device

An electron beam generator, a plasma processing apparatus, and a plasma processing method, the electron beam generator including a side insulator configured to surround the substrate support, the side insulator having an electron beam chamber therein; a first electrode embedded in the side insulator and adjacent to a first side wall of the electron beam chamber; a second electrode on a second side wall of the electron beam chamber; and a guide in an outlet of the electron beam chamber, the guide including slits through which electron beams generated in the electron beam chamber are transmittable into the process chamber.

Electron beam generator, plasma processing apparatus having the same and plasma processing method using the same

A semiconductor device includes a contact structure connected to an active region. A first insulating layer is disposed on a barrier dielectric layer and has a first hole connected to the contact structure. A second insulating layer is disposed on the first insulating layer and has a trench connected to the first hole. The second insulating layer has an extended portion along a side wall of the first hole. A width of the first hole less the space occupied by the extended portion is defined as a second hole. A wiring structure including a conductive material is connected to the contact structure. A conductive barrier is disposed between the conductive material and the first and second insulating layers. An etch stop layer is disposed between the first and second insulating layers and between the extended portion of the second insulating layer and a side wall of the first hole.

Semiconductor device

Disclosed are a method for cleaning a substrate, an apparatus for cleaning a substrate, and a method for fabricating a semiconductor device using the same. The method may include cleaning a substrate in a wet process, providing a supercritical fluid onto the substrate to remove moisture from the substrate, and cleaning the substrate in a dry process to remove defect particles from a substrate, which are produced by the supercritical fluid.

Substrate cleaning method, substrate cleaning apparatus, and method for fabricating a semiconductor device using the apparatus

A chamber has an upper housing and a lower housing and receives a reaction gas. A first plasma source includes electron beam sources providing electron beams into the upper housing to generate an upper plasma. A second plasma source includes holes generating a lower plasma within the holes connecting the upper housing and the lower housing. Radicals of the upper plasma, radicals of the lower plasma, and ions of the lower plasma are provided, through the holes, to the lower housing so that the lower housing has radicals and ions at a predetermined ratio of the ions to the radicals in concentration. The second plasma source divides the chamber into the upper housing and the lower housing. A wafer chuck is positioned in the lower housing to receive a wafer.

Plasma processing system, electron beam generator, and method of fabricating semiconductor device

A method of forming a semiconductor device includes: loading a wafer onto a susceptor, wherein the susceptor is disposed inside a chamber; heating the inside of the chamber; and rotating the susceptor, and first forming a film on the wafer by outputting a reactive gas and a carrier gas from an injector disposed at a sidewall of the chamber to form a semiconductor device having a first layer, wherein the first layer is manufactured under a first condition, wherein the injector includes a first outlet exposed within the chamber to discharge the carrier gas directly into the chamber and a second outlet exposed within the chamber to discharge the reactive gas directly into the chamber, wherein the first outlet is disposed below the second outlet.

Method of forming a semiconductor device with an injector having first and second outlets

A semiconductor device is provided. The semiconductor device includes first metal lines on a lower layer, a dielectric barrier layer provided on the lower layer to cover side and top surfaces of the first metal lines, an etch stop layer provided on the dielectric barrier layer to define gap regions between the first metal lines, an upper insulating layer on the etch stop layer, and a conductive via penetrating the upper insulating layer, the etch stop layer, and the dielectric barrier layer to contact a top surface of a first metal line. The etch stop layer includes first portions on the first metal lines and second portions between the first metal lines. The second portions of the etch stop layer are higher than the first portions.

Semiconductor device and method of fabricating the same

The present invention relates to a spark discharge generator. The spark discharge system of the present invention includes a plurality of columnar electrodes and a ground plate having a plurality of outlet holes at positions corresponding to the columnar electrodes. The use of the spark discharge generator enables the production of a three-dimensionally shaped nanostructure array on a large area in a uniform and rapid manner.

Multi-tip spark discharge generator and method for producing nanoparticle structure using same

The present invention relates to a process for preparing an electronic device comprising at least one layer selected from the group consisting of a upper electrode layer, a lower electrode layer, an organic layer and an inorganic layer, which comprises a step of introducing a nanoparticle layer or a nano/micro structure layer by adhering charged nanoparticles, before, after or during forming the layer.

Process for preparing nanoparticle embedded electronic device

Growing community of inventors

Seongnam-si, South Korea

Kyuhee Han