Applied Materials, Inc.

Varian Semiconductor Equipment Associates, Inc.

Kyuha Shim

Qintao Zhang

Sipeng Gu

Wei Zou

Rajesh Prasad

Deven Raj Mittal

Baonian Guo

Sony Varghese

Martin Jay Seamons

Pradeep Subrahmanyan

Nobuyuki Sasaki

Edwin A Arevalo

Tzu-Yu Liu

Qi Gao

Somchintana Norasetthekul

Shan Tang

Dennis Rodier

Lauren Liaw

Takaski Shimizu

Ryuichi Muira

Hiro Ito

Embodiments herein are directed to localized stress modulation by implanting a first side of a substrate to reduce in-plane distortion along a second side of the substrate. In some embodiments, a method may include providing a substrate, the substrate comprising a first main side opposite a second main side, wherein a plurality of features are disposed on the first main side, performing a metrology scan to the first main side to determine an amount of distortion to the substrate due to the formation of the plurality of features, and depositing a stress compensation film along the second main side of the substrate, wherein a stress and a thickness of the stress compensation film is determined based on the amount of distortion to the substrate. The method may further include directing ions to the stress compensation film in an ion implant procedure.

Localized stress modulation by implant to back of wafer

Approaches herein decrease nanosheet gate length variations by implanting a gate layer material with ions prior to etching. A method may include forming a dummy gate structure over a nanosheet stack, the dummy gate structure including a hardmask atop a gate material layer, and removing a portion of the hardmask to expose a first area and a second area of the gate material layer. The method may further include implanting the dummy gate structure to modify the first and second areas of the gate material layer, and etching the first and second areas of the gate material layer to form a treated layer along a sidewall of a third area of the gate material layer, wherein the third area is beneath the hardmask.

Ion implantation to reduce nanosheet gate length variation

A method may include providing a substrate having, on a first surface of the substrate, a low dielectric constant layer characterized by a layer thickness. The method may include heating the substrate to a substrate temperature in a range of 200&#xb0; C. to 550&#xb0; C.; and directing an ion implant treatment to the low dielectric constant layer, while the substrate temperature is in the range of 200&#xb0; C. to 550&#xb0; C. As such, the ion implant treatment may include implanting a low weight ion species, at an ion energy generating an implant depth equal to 40% to 175% of the layer thickness.

Techniques for improved low dielectric constant film processing

A method may include depositing a mask layer on a substrate using physical vapor deposition, wherein an absolute value of a stress in the mask layer has a first value; and directing a dose of ions into the mask layer, wherein the absolute value of the stress in the mask layer has a second value, less than the first value, after the directing the dose.

Techniques for forming low stress mask using implantation

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Andover, MA, United States of America

Kyuha Shim