Samsung Electronics Co., Ltd.

Kyu-Rie Sim

Gwan-Hyeob Koh

Dae-Hwan Kang

Kwang-woo Lee

Han-bin Noh

Jung-Hoon Park

Daewon Ha

Yoon-jong Song

Taehui Na

Jung Hyuk Lee

Jae-min Shin

Shin-Hee Han

A method of operating a resistive memory device to increase a read margin includes applying a write pulse to a memory cell such that the memory cell is programmed to a target resistance state, and applying a post-write pulse to the memory cell to increase a resistance of the memory cell that is in the target resistance state, the post-write pulse being applied as a single pulse having at least n stepped voltage levels, n being an integer equal to or more than 2, and an n-th stepped voltage level of the post-write pulse is set to be lower than a minimum threshold voltage level of the target resistance state that is changed by an (n&#x2212;1)-th stepped voltage level of the post-write pulse.

Method of operating resistive memory device to increase read margin

A variable resistance memory device includes memory cell stacks arranged in a first direction, the memory cell stacks including a first memory cell stack and a second memory cell stack. Each of the memory cell stacks includes a plurality of word lines, each word line of the plurality of word lines extending in a second direction intersecting the first direction and arranged in a third direction intersecting the first and second directions, and a memory cell connected to each of the plurality of word lines. Each of the memory cells includes a switching element and a variable resistance element. Each of the plurality of word lines of the first memory cell stack have a first thickness, in the first direction, of first word lines of the first memory cell stack is less than a second thickness, in the first direction, of each of the plurality of word lines of the second memory cell stack.

Variable resistance memory device

The inventive concept provides a memory device, in which memory cells are arranged to have a low variation in electrical characteristics and thereby enhanced reliability, an electronic apparatus including the memory device, and a method of manufacturing the memory device. In the memory device, memory cells at different levels may be covered with spacers having different thicknesses, and this may control resistance characteristics (e.g., set resistance) of the memory cells and to reduce a vertical variation in electrical characteristics of the memory cells. Furthermore, by adjusting the thicknesses of the spacers, a sensing margin of the memory cells may increase.

Memory device and electronic apparatus including the same

A variable resistance memory device includes first memory cells and second memory cells. The first memory cells are between first and second conductive lines, and at areas at which the first and second conductive lines overlap. The second memory cells are between the second and third conductive lines, and at areas at which the second and third conductive lines overlap. Each first memory cell includes a first variable resistance pattern and a first selection pattern. Each second memory cell includes a second variable resistance pattern and a second selection pattern. At least one of the second memory cells is shifted from a closest one of the first memory cells.

Variable resistance memory devices and methods of manufacturing the same

A resistance change memory device includes an array of resistance change memory cells, and a writing circuit configured to reset a selected memory cell to a high resistance state by supplying a RESET current to the selected memory cell in the array of resistance change memory cells in a program operation mode, wherein a level of the RESET current depends on a distribution of initial RESET currents for the array of resistance change memory cells.

Resistance change memory device and current trimming method thereof

A semiconductor device, a semiconductor module, an electronic apparatus and methods of fabricating and manufacturing the same are provided. The semiconductor device includes a lower interconnection formed on a substrate, a plurality of control patterns formed on the lower interconnection, a plurality of lower contact plug patterns formed on the control patterns, a plurality of storage patterns formed on the lower contact plug patterns, a plurality of upper electrodes formed on the storage patterns, and a plurality of upper interconnections formed on the upper electrodes. The lower contact plug patterns each include at least two contact holes having different sizes, a plurality of sidewall patterns formed on inner sidewalls of the two contact holes and wherein the sidewall patterns have different thicknesses from one another. The semiconductor device further includes a plurality of electrode patterns conformably formed on the inside of the sidewall patterns and having size errors less than 10%, and a plurality of filling patterns formed inside the electrode patterns and completely filling the inside of the contact holes.

Growing community of inventors

Hwaseong-si, South Korea

Kyu-Rie Sim