Qualcomm Incorporated

The Boeing Company

Kyu-Pyung Hwang

Young Kyu Song

Dong Wook Kim

Hong Bok We

Changhan Hobie Yun

Jae Sik Lee

Chin-Kwan Kim

Charles Muwonge

Terry R Vogler

Shiqun Gu

Ryan David Lane

Xiaonan Zhang

Victor Adrian Chiriac

Philipp Andreas Boettcher

Walid M Al-Bondak

Thomas D Mitchum

An assembly for electromagnetic interference (EMI) shielding to prevent incident radiation from penetrating through a gap to an interior of an aircraft includes an electromagnetic band gap (EBG) structure. The EBG structure has a patch-and-via array connected to a ground layer. The EMI shielding includes a conductive adhesive and is flexible for conforming attachment to curved aircraft surfaces. The shielding may be located on a deflector plate that is parallel to an adjacent aircraft surface, on the airframe surface opposite to the deflector plate, or in both locations. The assembly filters out penetrating electromagnetic energy and prevents highly resonant cavity mode build-ups of electromagnetic energy inside a nacelle or other enclosure effectively protecting electrical equipment in the interior.

RF filter device for aircraft nacelle access door gap

An electrical module assembly is provided. The electrical module assembly includes a circuit board with a first circuit-board surface and a second circuit-board surface defining a cavity, and an antenna disposed on the first circuit-board surface. The electrical module assembly also includes a wafer-level packaged (WLP) die embedded in the cavity. The WLP die has a first WLP die surface and a second WLP die surface. The second WLP die surface has electrical contacts thereon. The circuit board includes vias that extend from the antenna through the circuit board to the first WLP die surface to interconnect the antenna and the WLP die. The electrical module assembly further includes a second circuit board coupled to the second circuit-board surface, and coupled to the WLP die at the electrical contacts on the second WLP die surface of the WLP die.

Electrical module assembly with embedded dies

A method for modeling electromagnetic characteristics of a vehicle having electrical components comprising generating a parallel plate waveguide model and inserting a vehicle model for the vehicle within the parallel plate waveguide model. The vehicle model has a plurality of lumped ports corresponding to on-board electrical components. The method executes an electromagnetic field solver on a first and second waveguide ports and the lumped ports and determines a scaling factor between a first power level configured to excite the first and/or second waveguide ports and a second power level configured to excite the lumped ports. The electromagnetic field solver runs on the first and second waveguide and lumped ports, producing a first output data and the method produces a scattering parameter (S-parameter) model for the vehicle from the first output data that includes a plurality of S-parameter ports.

Method for high-intensity radiated field (HIRF) and electromagnetic pulse (EMP) analysis of a vehicle

A fire suppressing device including a torus container with a main body defining an interior chamber and a discharge port, the interior chamber configured to receive and retain metal organic framework materials. The fire suppressing device also includes an inductor coil extending through the interior chamber of the torus container and surrounding the metal organic framework materials. The inductor coil is configured to heat the metal organic framework materials to form a fire suppressing substance that is conveyed through the discharge port.

Fire suppressing device

In one or more embodiments, a method of manufacturing a high impedance surface (HIS) apparatus comprises patterning a first conducting layer on a core to form a first set of conducting pads, and patterning a second conducting layer on the core to form a second set of conducting pads. The method further comprises applying solder paste to each of the conducting pads of the second set of conducting pads. Also, the method comprises placing chip capacitors on the solder paste on the second set of conducting pads. In addition, the method comprises applying underfill between the chip capacitors. Also, the method comprises applying solder paste to each of the conducting pads of the first set of conducting pads. In addition, the method comprises placing chip inductors on the solder paste on the first set of conducting pads. Further, the method comprises applying underfill between the chip inductors.

Methods of manufacturing a high impedance surface (HIS) enhanced by discrete passives

In one or more embodiments, a high impedance surface (HIS) apparatus comprises a core; a first set of conducting pads, where a first side of the first set of conducting pads is connected to a first side of the core; and a second set of conducting pads, where a first side of the second set of conducting pads is connected to a second side of the core. The apparatus further comprises a plurality of chip inductors, where at least a portion of the chip inductors are connected to a second side of the first set of conducting pads; and a plurality of chip capacitors, where at least a portion of the chip capacitors are connected to a second side of the second set of conducting pads.

High impedance surface (HIS) enhanced by discrete passives

A resistor assembly is disclosed and comprises a first conductive trace, a second conductive trace, and a plurality of trimming bridges that electrically couple the first conductive trace to the second conductive trace. The resistor assembly also comprises a thin film resistor electrically coupled to the first conductive trace. The first conductive trace, the second conductive trace, the plurality of trimming bridges, and the thin film resistor are all part of a surface mounted layer of the resistor assembly. The plurality of trimming bridges are each removable to increase a resistance of the thin film resistor.

Thin film resistor having surface mounted trimming bridges for incrementally tuning resistance

A variable RF attenuator includes a substrate, a first microstrip trace, a first thin film resistor, a second microstrip trace, and a wire bond. The substrate includes a dielectric layer. The first thin film resistor is disposed on the substrate. The first microstrip trace is disposed on the substrate and the first thin film resistor. The second microstrip trace is disposed on the substrate and is uncoupled from the first microstrip trace. The wire bond extends from the second microstrip trace to a position on the first microstrip trace. The position is selected to tune RF attenuation over a conductive path defined by the first microstrip trace, the wire bond, and the second microstrip trace.

Variable radio frequency attenuator

A resistor assembly is disclosed and comprises a surface mounted layer comprising a first conductive trace, a second conductive trace, and a plurality of trimming bridges that electrically couple the first conductive trace to the second conductive trace. The resistor assembly also comprises a second layer disposed underneath the surface mounted layer. The second layer comprises an embedded thin film resistor electrically coupled to the surface mounted layer. The plurality of trimming bridges are each removable to increase a resistance of the embedded thin film resistor. The resistor assembly also comprises a plurality of vias that electrically couple the first conductive trace of the surface mounted layer to the embedded thin film resistor.

Many aspects of an improved IC package are disclosed herein. The improved IC package exhibits low-impedance and high power and signal integrity. The improved IC package comprises an IC die mounted on a multilayer coreless substrate. The thicknesses of prepreg layers of the coreless substrate are specific chosen to minimize warpage and to provide good mechanical performance. Each of the prepreg layers may have different coefficient of thermal expansion (CTE) and/or thickness to enable better control of the coreless substrate mechanical properties. The improved IC package also includes a vertically mounted die side capacitor and a conductive layer formed on the solder resist layer of the substrate. The conductive layer is formed such that it also encapsulates the vertically mounted capacitor while being electrically coupled to one of the capacitor's electrode.

Integrated circuit package comprising surface capacitor and ground plane

A passive discrete device may include a first asymmetric terminal and a second asymmetric terminal. The passive discrete device may further include first internal electrodes extended to electrically couple to a first side and a second side of the first asymmetric terminal. The passive discrete device may also include second internal electrodes extended to electrically couple to a first side and a second side of the second asymmetric terminal.

Capacitor structure for power delivery applications

A package on package structure may be formed by fabricating or providing a bottom package having a substrate, at least one die on top of the substrate, and bonding pads on the top of the substrate. Next, a frame is formed on the bonding pads and connected to the bonding pads. Next, a package material is molded over the top of the substrate to encapsulate the frame, the die, and the pads or substantially encapsulates these components. Next, a portion of the molded package material is removed to expose at least a portion of the frame. The exposed frame portions are formed such that a desired fan in or fan out configuration is obtained. Next, a non-conductive layer is formed on the exposed frame. Last, a second package having a die or chip is connected to the exposed portion of the frame to form a package on package structure.

Semiconductor package on package structure and method of forming the same

Embodiments contained in the disclosure provide a method and apparatus for testing an electronic device. An electronic device is installed in a test socket guide. A pusher tip applies a load to the guided coaxial spring probes and forces contact with pads on the device. Test and ground signals are routed through the device and test socket. The apparatus includes a socket having at least one guided coaxial spring probe pin. A socket guide shim is positioned between the receptacle for the electronic device and the socket. A socket guide aids positioning. A pusher tip is placed on the side opposite that of the guided coaxial spring probe pins. The pusher tip mates with a pusher shim and the pusher spring. A top is then placed on the assembly and acts to compress the pusher spring and engage the guided coaxial spring probe pins with the pads on the device.

Known good die testing for high frequency applications

The present disclosure provides semiconductor packages and methods for fabricating PoP semiconductor packages. The PoP semiconductor package may comprise a first semiconductor package, the first semiconductor package comprising an anodized metal lid structure comprising (i) a central cavity having a central cavity opening direction and (ii) at least one perimeter cavity having a perimeter cavity opening direction facing in an opposite direction of the central cavity opening direction, a first semiconductor device arranged in the central cavity of the anodized metal lid structure, a redistribution layer electrically coupled to the first semiconductor device, wherein a conductive trace formed in the redistribution layer is exposed to the at least one perimeter cavity, and solder material arranged in the at least one perimeter cavity, and a second semiconductor package, the second semiconductor package comprising at least one conductive post, wherein the at least one conductive post is electrically coupled to the solder material arranged in the at least one perimeter cavity.

Low profile reinforced package-on-package semiconductor device

Some novel features pertain to a capacitor structure that includes a first conductive layer, a second conductive layer and a non-conductive layer. The first conductive layer has a first overlapping portion and a second overlapping portion. The second conductive layer has a third overlapping portion, a fourth overlapping portion, and a non-overlapping portion. The third overlapping portion overlaps with the first overlapping portion of the first conductive layer. The fourth overlapping portion overlaps with the second overlapping portion of the first conductive layer. The non-overlapping portion is free of any overlap (e.g., vertical overlap) with the first conductive layer. The non-conductive layer separates the first and second conductive layers. The non-conductive layer electrically insulates the third overlapping portion and the fourth overlapping portion from the first conductive layer.

Growing community of inventors

San Diego, CA, United States of America

Kyu-Pyung Hwang