Samsung Electronics Co., Ltd.

Kyu-Pil Lee

Kye-Hee Yeom

Joon Seong Kang

Yun-Seung Shin

Yong-jik Park

Jong-Jik Park

Integrated circuit memory devices include a memory cell field effect transistor in an integrated circuit substrate, a conductive plug that electrically contacts the memory cell field effect transistor and a titanium nitride bit line that electrically contacts the conductive plug opposite the memory cell filed effect transistor. Titanium nitride also may be used to electrically contact field effect transistors in the peripheral region of the integrated circuit memory device. Titanium nitride can be used as a bit line metal instead of conventional tungsten, and as a conductive plug to contact both p -type and n -type source/drain regions in the peripheral region of the memory device. The titanium nitride conductive plugs and bit lines may be formed simultaneously.

Methods of fabricating integrated circuit memories including titanium nitride bit lines

A semiconductor device and method for manufacturing the same includes a plurality of memory cells, each cell having a transistor formed on a first semiconductor substrate and comprising first and second impurity regions and a gate electrode, and a capacitor comprising a first electrode connected with the first impurity region of the transistor and a second electrode formed on the first electrode with a dielectric film disposed therebetween, wherein a channel region formed between the first impurity region and the second impurity region of the transistor is vertically located on the capacitor, and a contact hole connecting the second impurity region of the transistor with the bit-line is vertically located on the channel region, thus achieving the cell area required for one-giga-bit memory devices and beyond and enabling increased capacitance.

Method for manufacturing a semiconductor device

Integrated circuit memory devices include a memory cell field effect transistor in an integrated circuit substrate, a conductive plug that electrically contacts the memory cell field effect transistor and a titanium nitride bit line that electrically contacts the conductive plug opposite the memory cell filed effect transistor. Titanium nitride also may be used to electrically contact field effect transistors in the peripheral region of the integrated circuit memory device. Titanium nitride can be used as a bit line metal instead of conventional tungsten, and as a conductive plug to contact both p,-type and n,-type source/drain regions in the peripheral region of the memory device. The titanium nitride conductive plugs and bit lines may be formed simultaneously.

Integrated circuit memory devices including titanium nitride bit lines

According to the present invention, a conductive pad for a self-aligned direct contact and a self-aligned buried contact is formed of a first pad and a second pad, in twice, wherein the self-aligned direct contact and the self-aligned buried contact connect respectively a bit line/storage electrode to a semiconductor substrate. The first pad and the second pad are formed by combining a reverse active type self-aligned contact (RAT-SAC), a contact type self-aligned contact (CT-SAC), and an epitaxial growth processes. Thus, it is prevented that a shoulder portion of a gate electrode is overetched to create electrical short of pad to gate, a size of a pad is limited to a spacing between gate electrodes, a pad and a semiconductor substrate are not electrically connected each other (not-open), and electrical connection is created by lack of margin between BCs, in case of using only one process selected from a group consisting of the RAT-SAC process, the CT-SAC process, and the epitaxial growth processes.

Method for fabricating conductive pad

A semiconductor memory device and a fabricating method therefor are disclosed. The semiconductor memory device includes a peripheral region and a core region containing a transistor with at least a p&plus; impurity region. An inter-layer insulating layer is formed on an entire surface of a semiconductor substrate. Then the insulating layer is etched by using a contact forming mask until the surface of the p&plus; impurity region of the core region is exposed, so as to form contact holes. The contact holes are then filled with a metal to form contacts so as to be electrically connected to the semiconductor substrate. The present invention solves the conventional problem that the contact plug reacts with the impurity ions of the p&plus; impurity region during the heat treatment, thereby increasing the contact resistance. That is, in the present invention, the contact for the wiring on the semiconductor substrate of the p&plus; impurity region is directly formed after the formation of the memory cells in the cell region at a high temperature. Therefore, the succeeding high temperature process steps are simplified, and therefore, the metal layer is prevented from being reacted with the impurity ions, thereby preventing the increase of the contact resistance. Thus, a stable performance of the semiconductor device is ensured.

Semiconductor memory device, and method for fabricating thereof

A novel method for fabricating a semiconductor memory device wherein the interconnection wiring line in a core/peripheral region is formed before bit line in a cell array region formation, thereby preventing damaging of the interconnection wiring line caused during forming the bit line and improving the process margin in the core/peripheral region.

Method for fabricating a semiconductor device

A method of forming self-aligned contact holes of a semiconductor device presents bridging from occurring between contacts formed in the holes. First, gate electrode structures are formed on a semiconductor substrate. Next, an interlayer insulating film is formed over the gate electrode structures. The interlayer insulating film is formed by forming a first oxide layer of a reflowable material over the semiconductor substrate and gate electrode structures, planarization etching the first oxide layer until the upper portions of the gate electrode structures are uncovered, and then forming a second oxide layer on the planarized upper surface of the first oxide layer. The second oxide layer is selected to have a wet etch rate that is lower than that of the first oxide layer. Then, the insulating film is etched to form a contact hole between gate electrode structures. Finally, a self-aligned contact electrically connected with the semiconductor substrate is formed by filling the contact hole with conductive material.

Method of manufacturing a semiconductor device having self-aligned

A semiconductor device is fabricated having contact holes formed in an interlayer insulator and on impurity diffusion regions positioned on either side of an isolator, The contact holes are arranged so as not to be disposed along a shortest line path across the isolator. This arrangement isolating interval and provides a structure which can realize higher packing density and improved reliability.

Semiconductor device having an improved packing density and high

The semiconductor memory device with a stacked capacitor is disclosed. When the mis-align is generated in forming contact region 42 for contact between the storage electrode of the stacked capacitor and the source region 34, the ion-implantation process, with the same conductive type as that of the source region, is carried out, to form the another source region 48 under the bottom surface of the contact region 42, wherein the polysilicon layer on the substrate is used as the mask. The successive ion-implantation provides the diffusion region 58 capable of wholly surrounding the another source region 48, wherein the diffusion region 58 contains higher concentration than that of the substrate and simultaneously lower than that of the source region, with the same conductive type as that of substrate. On the other hand, when no mis-align is generated, the semiconductor memory device further comprises another diffusion region 58a formed below the source region 34a, the diffusion region 58a having the opposite conductive type to that of the source region. Thereby the memory device is provided with the improvement of the refresh characteristic and with decrease of the soft error rate.

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Kyunggi-do, South Korea

Kyu-Pil Lee