Skhynix Inc.

Kyu Nam Lim

Woong Ju Jang

Ki Myung Kyung

Mun Phil Park

Hong Sok Choi

Sun Hwa Park

An embodiment of the present technology includes a memory device and a method of operating the memory device. The memory device includes a memory block, a peripheral circuit configured to increase a threshold voltage of memory cells selected among memory cells included in the memory block according to logic data, detect low-level cells having a threshold voltage higher than a reference voltage among memory cells having a threshold voltage lower than a verify voltage at a first time within a verify time set according the number of bits included into the logic data, and detect high-level cells having a threshold voltage higher than the verify voltage at a second time after the first time, and a control circuit configured to control the peripheral circuit in response to a command.

Memory device and method of operating the memory device

A sense amplifier may include an amplifying section configured to amplify data of a segment line pair when an enable signal is activated and output amplified data to a local line pair, and including latches electrically coupled in a cross-coupled type. The sense amplifier may include a switching section configured to selectively electrically couple the segment line pair and the local line pair in response to an input/output switch signal.

Sense amplifier and semiconductor device including the same

An input/output sense amplifier is configured to amplify data inputted through a pair of local transmission lines in response to a sense amplifier enable signal and a test mode signal, output the data through a global transmission line, generate a control signal by sensing whether the data have been amplified, and halt amplification of the data in response to the control signal when amplification is completed.

Input/output sense amplifier and semiconductor apparatus including the same

A semiconductor memory device includes a switching unit coupled between a local sense amplifier and a bit line sense amplifier and configured to be turned on in response to a switching signal which is enabled in synchronization with an enable signal for enabling the local sense amplifier and disabled at a time point where a preset period passes after a first power for enabling the bit line sense amplifier is precharged.

Semiconductor memory device

A semiconductor memory apparatus includes: a first sense amplification unit including first and second inverters configured to be driven to voltage levels of a power driving signal and a ground driving signal and forming a latch structure between a bit line and a bit line bar; and a second sense amplification unit including first and second transistors configured to be driven to the voltage level of the ground driving signal and forming a latch structure between the bit line and the bit line bar when an activated switching signal is applied, wherein a threshold voltage of the second sense amplification unit is set lower than that of the first sense amplification unit.

Semiconductor memory apparatus

A sense amplifier is configured to transfer data on a first data I/O line to a second data I/O line or to transfer data on the second data I/O line to the first data I/O line. The first data I/O line is substantially continuously coupled to the second data I/O line during an active operation.

Growing community of inventors

Icheon-si, South Korea

Kyu Nam Lim