Samsung Electronics Co., Ltd.

Kyu-Nam Lim

Sang-Seok Kang

Jong-hyun Choi

Jei-Hwan Yoo

Yun-Sang Lee

Jae-Yoon Shim

Seong-Jin Jang

Jong-Won Lee

Gi-Won Cha

Young-Gu Kang

Sang-suk Kang

Young-gu Kang

Sang-Suk Kang

Bum-Jae Lee

Su-A Kim

Kyu-Hyun Kyung

Provided is a circuit and method of generating a boosted voltage while maintaining a constant difference between the boosted voltage and an array reference voltage when the array reference voltage is varied in a normal mode, a test mode, and a burn-in test mode of a semiconductor device. The boosted voltage generating circuit comprises a sensing signal generating circuit which generates a sensing signal, a pulse generating circuit which generates a driving signal in response to the sensing signal, and a pumping circuit which generates the boosted voltage in response to the driving signal to control a word line of a semiconductor device. The sensing signal generating circuit comprises a comparator which includes a first input terminal, a second input terminal for receiving a reference voltage, and an output terminal for outputting the sensing signal, a resistor coupled between the boosted voltage and the first input terminal, and a constant current source coupled between the first input terminal and a ground voltage.

Circuit and method of generating a boosted voltage

A power up signal generator includes a signal converter for converting an applied external source voltage to a voltage applied at a trigger node when the external source voltage rises to a first threshold, and a current source for flowing a reference current from the trigger node. A first inverter connected to the trigger node outputs a low level signal when the trigger node voltage reaches a second threshold. A second inverter outputs a power up signal after receiving the low level signal from the first inverter. The signal converter may include a PMOS transistor configuration, such that the trip voltage of the power up signal generator is dependent only on a single MOSFET transistor threshold voltage.

Power up signal generator

Provided is a semiconductor device that is insensitive to a change in a power supply voltage, inconsistencies in a manufacturing process, and a change in temperature and provides for a rapid read data operation. The semiconductor device includes a first read signal generator, a second read signal generator, and a voltage input/output sense amplifier. The first read signal generator generates a first read signal for sampling data in response to an enable signal of a column selection line. The second read signal generator generates a second read signal including a plurality of pulses during an enabling period of the first read signal in response to the first read signal. The voltage input/output sense amplifier receives a data value output from a memory cell, amplifies the data value in synchronization with the column selection line, and samples the data value in synchronization with enabling signals of the second read signal.

Semiconductor device having input/output sense amplifier for multiple sampling

A semiconductor memory device having a hierarchical structure of data input/output lines and a precharge method thereof. A precharge method in a semiconductor memory device having a hierarchical structure includes precharging the global input/output line pairs with half of a memory cell array voltage, and precharging the local input/output line pairs with the half of the memory cell array voltage.

Semiconductor memory device having hierarchical structure of data input/output line and precharge method thereof

A semiconductor memory device having a bit line sense amplifier connected to a bit line pair may include a precharge part to precharge first and second drive nodes of the bit line sense amplifier to an equal voltage level. The device may include a switching part operatively connecting the first and second precharge nodes to the first and second drive nodes in response to sense amplifier drive signals applied during a data non-access mode. To drive power in the bit line sense amplifier, the precharge voltage may be applied in a precharge state to precharge the first and second drive nodes to the equal voltage level, the device may shift from the precharge state to an operational state to cut off the applied precharge voltage, and driving voltages may be applied to the first and second drive nodes to power the bit line sense amplifier of the device.

Semiconductor memory device having improved bit line sensing operation and method for driving power in a bit line sense amplifier of the semiconductor memory device

A semiconductor memory device with a bit line sense enable signal generating circuit is disclosed. The semiconductor memory device includes a word line selection signal generating circuit for generating a word line selection signal for selecting a word line; a delay circuit for generating a delayed signal by delaying a signal to the same extent of time period which is needed for the word line selection signal generating circuit to generate the word line selection signal; and a Schmitt trigger for generating a word line enable detecting signal by receiving an output signal from the delay circuit and that is connected to a power supply voltage which has the same voltage level as the voltage level used to enable the word line. The bit line sense enable signal generating circuit in the present invention occupies a relatively smaller layout area than that of conventional semiconductor memory devices. Furthermore, the generating circuit generates a bit line sense enable signal with constant delay time that is immune from process changes, voltage fluctuations, and temperature fluctuations.

Semiconductor memory device including a delaying circuit capable of generating a delayed signal with a substantially constant delay time

In a semiconductor memory device, a circuit for controlling a voltage level applied to a bit line isolation circuit preferably includes a memory cell connected between a cell bit line pair and a word line; a bit line pre-charge circuit; a sense amplifier bit line pre-charge circuit; a charge transfer circuit connected between the cell bit line pair and the sense amplifier bit line pair; a first sense amplifier circuit for amplifying a voltage of the sense amplifier bit line pair to a first voltage in response to a first control signal; and a second sense amplifier circuit for amplifying the voltage of the sense amplifier bit line pair to a second voltage in response to a second control signal. The combination of the two-stage sense amplifier ciruitry allows for the accurate determination of minimally-different logical voltage levels and minimized circuit area.

Semiconductor memory device and bit line sensing method thereof

Integrated circuits are provided that include a voltage control circuit that is configured to adjust a circuit voltage that is outside a predetermined circuit voltage specification to within the predetermined circuit voltage specification so that the integrated circuit device is no longer defective. Integrated circuits are also provided that include a signal time delay control circuit that is configured to adjust a circuit delay time that is outside a predetermined circuit delay time specification to within the predetermined circuit delay time specification so that the integrated circuit device is no longer defective. Corresponding methods of operation are also provided.

Voltage and time control circuits

An internal power voltage generating circuit capable of accurately adjusting a level of an internal power voltage in response to an overshoot of the internal power voltage. In one embodiment, the circuit comprises an internal power voltage generator for generating an internal power voltage to an internal power voltage generating terminal, first and second resistor devices, serially connected between the internal power voltage generating terminal and a ground voltage, for distributing the internal power voltage and for generating a distributed voltage to a distributed voltage generating node, and a current discharging device, connected between the internal power voltage generating terminal and the ground voltage, for discharging current from the internal power voltage generating terminal to the ground voltage in response to the distributed voltage.

Internal power voltage generating circuit

An input buffer circuit simultaneously supports a low voltage interface and a general low voltage transistor-transistor logic (LVTTL) interface and operates at high speed. In the input buffer circuit, a self bias voltage generated by a self biased differential amplification circuit is used not only for tracking a common mode input voltage in the differential amplification circuit but also for controlling the current of a current source and/or sink that controls the current used in the differential amplification circuit. Accordingly, the self bias voltage remains at a substantially uniform level. Therefore, the entire transconductance gain gm of the differential amplification circuit is substantially uniform regardless of the change in a reference voltage input to the differential amplification circuit. As a result, a low voltage interface characteristic is improved. The input buffer circuit further can further include a swing width control circuit that responds to an inverted signal generated from the output signal of the differential amplification circuit and prevents the voltage swing of the output signal from becoming excessively large. This reduces skew and thus improves the operating speed of the input buffer.

Input circuit buffer supporting a low voltage interface and a general low voltage transistor logic(LVVTL) interface

A device according to the invention includes memory cells and a current sense amplifier. It also includes a feedback circuit to adjust a gain of the current sense amplifier. The gain is adjusted depending on relative delays of data stored in different ones of the memory cells to be read on the current sense amplifier.

Semiconductor memory device and data read method thereof

A high voltage generating circuit includes a standby high voltage generating means and an active high voltage generating means. The standby high voltage generating means detects a level of a high voltage in both a standby mode and an active mode to boost the high voltage when the level of the high voltage is lower than a predetermined level. The active high voltage generating means varies a voltage boosting ability responsive to a control signal when an active command is applied in the active mode to thereby boost the level of the high voltage. The active high voltage generating means also detects whether the level of the high voltage is lower than the predetermined level to adjust a level of the control signal.

High voltage generating circuit and method

A cross-coupled transistor pair includes separately arranged first and second active areas. A gate area of a first transistor is arranged symmetrically on portions of the first and second active areas. A gate area of a second transistor is also arranged symmetrically on portions of the first and second active areas. A first signal line extends between drain areas of the first transistor and the gate area of the second transistor. A second signal line extends between drain areas of the second transistor and the gate area of the first transistor. Metal lines can be provided to connect a source voltage, data signal lines, or control signals to common source areas of the first and second transistors. Methods for constructing cross-coupled transistor pairs are also provided.

Cross-coupled transistor pair

In a voltage generator having a voltage level detector, an oscillator, and a voltage pump, the voltage level detector comprises an amplifier, which, in combination with a first and a second linear current source, provides accurate control of an output voltage of the voltage generator. When a sensed voltage deviates around a reference voltage, a differential detection by the amplifier of this deviation causes the oscillator and the voltage pump to provide a corresponding increase or decrease in the magnitude of an output voltage in order to compensate for the deviation. Use of the amplifier and a predetermined reference voltage allows for an accurate threshold detection level for low-voltage, high-speed operation of the voltage generator. The present invention can be used in both positive and negative voltage generators.

Voltage level detector and voltage generator using the same

An apparatus and a method are disclosed for package level burn-in test circuit in semiconductor devices. The apparatus includes a package burn-in register, a test voltage generator for the package level burn-in test, a burn-in master signal generator, and a burn-in test circuit. The package burn-in register stores a package burn-in set-order from the outside and generates a package burn-in set-signal. The test voltage generator generates burn-in test voltages in response to the package burn-in set-signal and to address signals through first address terminals from the outside. The burn-in master signal generator generates a burn-in master signal by combining and receiving the second address signal form first address terminals, a wafer burn-in enable signal from a control signal input terminal, and the package burn-in set-signal. After receiving the burn-in master signal, multiple address signals from multiple third address terminals, and the test voltages for the package level burn-in test, the burn-in test circuit performs a package level burn-in test.

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Suwon, South Korea

Kyu-Nam Lim