Samsung Electronics Co., Ltd.

Kyu-Min Park

Jun-Ho Jo

Do-Han Kim

Byoung-sul Kim

Byoungsul Kim

Seung-Woo Lim

Hak-Yong Lee

Hakyong Lee

A storage system includes a processor configured to request a write operation of first data corresponding to a first logical address, and requests a write operation of second data corresponding to a second logical address, a memory module including a nonvolatile memory device configured to store the first data and the second data, and a controller configured to convert the first logical address into a first device logical address, and converts the second logical address into a second device logical address based on the first device logical address and a size of the first data, and a storage device configured to store the first data in the storage device based on the first device logical address, and store the second data in the storage device based on the second device logical address.

Storage system including nonvolatile memory module for converting random logical addresses to sequential logical addresses and operating method of the nonvolatile memory module

A memory device includes an interface unit and a memory unit. The interface unit receives a clock signal, a command signal and a data signal, internally adjusts input impedance based upon at least one of the command signal and the clock signal, and generates internal control signal of the memory device based upon the command signal and data signal. The memory unit performs read/write operations based upon the internal control signal.

Memory device and memory system including the same

A test mode control circuit is provided to strictly allow entry into a test mode or prevent a boot failure from occurring during a boot operation for a built-in parallel bit test. The test mode control circuit includes a latch, a real entry signal detector, an entry determinator, and a mode control signal generator. When a real entry signal is detected, the entry signal determinator generates an entry determination signal and a test mode control signal is obtained from the mode control signal generator.

Test mode control circuit in semiconductor memory device and test mode entering method thereof

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Bucheon-si, South Korea

Kyu-Min Park