Samsung Electronics Co., Ltd.

Hyundai Motor Company

Kia Motors Corporation

Kyu Jin Lee

Chun Hyuk Lee

Seong Ik Hong

Sang Hoon Yoo

Chang Hoon Kwak

Cheol Jun Yoo

Jang Hyo Lee

Do Soo Jeong

Wan Gyan Choi

Wan Gyun Choi

Il Han Park

Young Do Kweon

Hyeon J Jeong

Il Ung Kim

Tae Gyeong Chung

Jae June Kim

In Ho Hyun

Sang Hyeog Lee

Ii Woo Park

Hyung Jik Byun

A system and method for charging a plug-in hybrid vehicle can improve the on-board charging efficiency of the plug-in hybrid vehicle by adjusting a frequency of operation of a cooler when cooling an on-board charger (OBC) by circulating coolant when the temperature of the OBC rises while a high-voltage battery is being charged. The operations of a water pump and a radiator fan are controlled by determining whether the voltage of the high-voltage battery is within or out of a reference voltage range in which the on-board charging of the high-voltage battery is performed. This consequently prevents power from being unnecessarily consumed by operation of the cooler, such that the efficiency of charging is improved and the OBC is properly cooled.

System and method for charging plug-in hybrid vehicle

There are provided a phosphor film, a method of manufacturing the same, and a method of coating an LED chip with a phosphor layer. The phosphor film includes: a base film; a phosphor layer formed on the base film and obtained by mixing phosphor particles in a partially cured resin material; and a cover film formed on the phosphor layer to protect the phosphor layer.

Phosphor film, method of manufacturing the same, coating method of phosphor layer, method of manufacturing LED package and LED package manufactured thereby

Phosphor film, method of manufacturing the same, coating method of phosphor layer, method of manufacturing LED package, and LED package manufactured thereby

A multi-chip package includes a substrate with a chip mounting area and a first chip positioned in the mounting area. A spacer is attached to the active surface of the first chip and has a thickness to allow space for wire-bonding the first chip's active surface to the substrate. A second chip is attached to the spacer over the first chip. Conductive metal wires electrically connect the first and second chips to the substrate. A package body is formed by encapsulating the first and second chips and the conductive metal wires. Ends of the spacer extend to the edge the package body. External connection terminals are attached to the bottom surface of the substrate and a method for the manufacturing thereof.

Multi-chip package having spacer that is inserted between chips and manufacturing method thereof

An active surface of a semiconductor chip is attached to the bottom surface of a flexible circuit board having a central opening. Input/output pads on the active surface of the chip are electrically connected to a circuit layer on the top surface of the flexible circuit board through the opening. The semiconductor chip package can thus be of a size on the order of that of the chip. The circuit layer on the circuit board includes bonding pads for receipt of metal wires, land pads for receipt of terminals, and circuit traces connecting the pairs of the bonding and land pads, respectively. The input/output pads, the bonding pads, and the wires are encapsulated in an encapsulant formed by dispensing a liquid resin having a certain viscosity into the opening in the flexible circuit board. A dam around the opening prevents the liquid resin from overflowing. The flexible circuit board may further include a protective layer for protecting the circuit traces, a stiffener, or an adhesive layer thereunder. The protective layer may have a groove in which the dam is formed.

Semiconductor chip package using flexible circuit board with central opening

A package for a semiconductor chip including a plurality of input/output pads includes an insulating layer and a plurality of conductive traces. The insulating layer has a first surface for bonding with the surface of the semiconductor chip so that the input/output pads are exposed adjacent the insulating layer. The conductive traces are provided on a second surface of the insulating layer opposite the first surface wherein each of the conductive traces corresponds to a respective one of the input/output pads. In particular, the conductive traces are adapted to receive a plurality of bonding wires each of which corresponds to a respective one of the input/output pads. Accordingly, each of the bonding wires can be bonded at a first end to the respective input/output pad and at a second end to the respective conductive trace. Furthermore, the input/output pads can be on an interior portion of the surface of the semiconductor chip, and the insulating layer can have an opening therein for exposing the input/output pads. Accordingly, a dam on the second surface of the insulating layer can be provided around the opening wherein each of the conductive traces extends from adjacent the opening under the dam to a portion of the insulating layer outside the dam. Related methods and assemblies are also discussed.

Wire bond packages for semiconductor chips and related methods and

A method for manufacturing a known good die array('KGD' array ), which includes the steps of: (a) forming a plurality of circuit patterns, and bonding pads to match solder bumps on a wafer; (b) providing solder bumps on the bonding pads; (c) forming metal layers for wire-bonding on the solder bumps; (d) dividing the wafer having metal layers into respective individual circuit pattern unit dies; (e) holding at least one die in a die holder for testing; (f) wire-bonding circuit contacts of the die holder with the metal layers using wires; (g) testing the die which is electrically interconnected with the die holder; and (h) removing simultaneously the metal layer on the solder bumps for wire bonding and the wires from the die to give a known good die array having solder bumps.

Method for manufacturing known good die array having solder bumps

A semiconductor device package contains column leads which are electrically connected to a chip. The column leads, chip and electrical connection means are encapsulated to form a package body, from which the column leads extend for connection to a substrate such as a printed circuit board. A lead frame for the column leads can be formed by etching the column leads and a die pad out of a section of column lead material with a polyimide layer backing. Alternatively, a lead frame having parallel side rails on either side of a die pad can be used as an assembly frame for rows of column leads. Mass production of this package body using either type of lead frame produces high reliability packages in a simple and cost-effective way.

Semiconductor device package structure having column leads and a method

A method for manufacturing a chip-size package and the chip-size package produced by the method uses first and second lead frames which are prepared by a stamping process. The first lead frame has leads with receiving parts, and the leads are integrally formed with lengthwise side rails of the lead frame. The second lead frame has external connections which align with the receiving parts of the leads when the second lead frame is positioned on top of the first lead frame and attached thereto. Guide holes located on the crosswise side rails of both lead frames can be used to easily align the two lead frames. A semiconductor chip is then adhered to the underside of the first lead frame, and the bonding pads of the semiconductor chip are electrically connected to the leads of the first lead frame. Then the two lead frames and the chip are encapsulated, with only the external connections of the second lead frame remaining exposed to the outside. Solder balls are then attached to the external connections for mounting onto a substrate. This chip-size package is inexpensive to produce, because the first and second lead frames can be produced by a stamping process, which is less complex and cheaper than the conventional half-etching process.

Chip-size package (CSP) using a multi-layer laminated lead frame

A stacked semiconductor package including a plurality of semiconductor devices stacked over one another and having outer leads, which are extended from sides of the devices and bent downwardly. A plurality of supports are vertically interposed between the outer leads. The supports electrically connect the outer leads in vertical direction only.

Stacked semiconductor package having supporting bars and a socket

An appartus for testing bare semiconductor chips, especially for burn-in testing, includes a chip holding socket which comprises a substrate portion having at least one pair of opposing grooves formed along respective edges thereof. A pair of resilient elongate members are inserted into the grooves, and act to hold a respective bare chip in the holding socket. Preferably, a plurality of such holding sockets are mounted and electrically connected to a main test board, by which test signals are provided to test the bare semiconductor chips. A method for manufacturing such a testing apparatus is also disclosed herein.

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Seoul, South Korea

Kyu Jin Lee