Samsung Electronics Co., Ltd.

Lg Electronics Inc.

Choongwae Pharma Corporation

Kyu-Hyun Lee

Byung-Jun Park

Yoon-Soon Chun

Jae-Yong Park

Jae-Goo Lee

Sang-sup Jeong

Chang-hyun Cho

Ki-Seok Lee

Jung-hwan Park

Jay-Bok Choi

Yun-Jae Lee

Young-jin Choi

Ki-Hyun Lyu

Ju-Yong Lee

Won-Seong Lee

Jae-Kyun Lee

Jung-Hoan Kim

Sang-Heon Lee

Kye-Hyun Kim

Kwang-Youl Chun

Jeong-hoon Oh

Mi-Jeong Jang

Ju-Young Huh

Jae-Young Jung

Ji-Woong Hong

Jong-Woo Park

Hyo-Jin Park

A semiconductor memory device and a manufacturing method of the semiconductor memory device are provided. The semiconductor memory device can include a substrate in which a cell area and a peripheral area are defined, a first gate insulating layer on the peripheral area, and a poly gate layer on the first gate insulating layer to form a combined stack, wherein the combined stack of the first gate insulating layer and the first poly gate layer is absent from the cell area.

Semiconductor memory devices and manufacturing methods thereof

A semiconductor device includes a plurality of parallel-trenches that are parallel to each other, a plurality of intersect-trenches that are parallel to each other, a plurality of active regions that are confined by the parallel-trenches and the intersect-trenches, a plurality of lower conductive lines that cross the active regions, a plurality of upper conductive lines that are parallel to each other, that cross the lower conductive lines, and that cross over the active regions, and data storage elements connected to the active regions. Each of the parallel-trenches and the intersect-trenches is a straight line. The parallel-trenches cross the upper conductive lines and form a first acute angle with the upper conductive lines. The intersect-trenches cross the parallel-trenches and form a second acute angle with the parallel-trenches.

Semiconductor device having line-type trench to define active region and method of forming the same

Disclosed herein are a semiconductor device and a method of manufacturing the same that increases the reliability of these devices as size design limitations decrease. Generally, a first insulating film, and wiring, including conductive film patterns and second insulating film patterns are formed on a substrate. Third insulating film patterns including a silicon-oxide-based material are formed on sidewalls of the wiring, and contact patterns and spacers on the sidewalls thereof for defining contact hole regions are formed on the wiring. The contact holes contact surfaces of the third insulating film patterns and pass through the first insulating film. Thus, the thickness of a second insulating film pattern used in the wiring can be minimized, thereby increasing a gap-fill margin between the wiring. A parasitic capacitance between the wiring can be reduced because silicon oxide spacers with a low dielectric constant are formed on sidewalls of the wiring.

Semiconductor device and method of manufacturing the same

Embodiments of methods of fabricating protected contact plugs include forming an electrically insulating layer having a contact hole therein, on a semiconductor substrate and then forming an electrically conductive lower barrier layer that lines at least an upper portion of a sidewall of the contact hole. This lower barrier layer may comprise titanium nitride (TiN). A step is also performed to form an electrically conductive contact plug that extends in the contact hole, is electrically coupled to the lower barrier layer and protrudes above the electrically insulating layer. The contact plug may comprise tungsten (W). An electrically conductive upper barrier layer is then formed that extends on a protruded upper surface of the contact plug and on a surface of the lower barrier layer. A step may then be performed to pattern the upper barrier layer to define an electrically conductive barrier spacer that extends on a sidewall or end of the lower barrier layer and define an upper barrier layer cap on the protruded upper surface of the contact plug.

Semiconductor devices having protected plug contacts and upper interconnections

A DRAM device in which a portion of bit lines has enlarged width portions at a portion of a peripheral/core area to be connected with upper layered circuit wiring through metal contacts, includes spacers formed of a layer of material having an etch selectivity with respect to a bit line interlayer insulating layer deposited after said bit lines are formed, and disposed on sides of an upper surface of each said enlarged width portion to protect sides of said enlarged width portions; an interlayer insulating layer and at least a portion of an etch stop layer disposed between said bit lines and transistors of a substrate; and metal contact pads formed along with bit line contact plugs to pass through said interlayer insulating layer and said etch stop layer.

DRAM device

A method of forming self-aligned contacts in a semiconductor device wherein a silicon nitride layer and a polysilicon layer are formed on a gate electrode layer. The polysilicon layer, the silicon nitride layer, and the gate electrode layer are etched to form gate electrode configurations. Sidewall spacers are formed on both sidewalls of the gate electrode configurations. An oxide layer is then deposited on the resulting structure. Selected portions of the oxide layer are etched to form self-aligned contacts that expose the semiconductor substrate. Because the polysilicon has an excellent etch selectivity with respect to the oxide layer, the gate electrode layer can be sufficiently protected during the etching of the oxide layer resulting in a good shoulder margin at the exposed upper edges of the silicon nitride gate mask layer.

Method of forming self-aligned contacts in a semiconductor device

The present invention provides a method of eliminating or covering a defect source in a wafer edge region for semiconductor fabrication. During the etching process of a sacrificial oxide layer for storage node openings, the sacrificial oxide layer has a rumple topology in the wafer edge region due to etching non-uniformity of a photoresist layer formed on the sacrificial oxide layer. Subsequent deposition of a conductive layer and planarization etching, the conductive layer undesirably remains at the wafer edge region as a defect source. Such conductive contaminant particles dislodge, causing many problems in the wafer main region. The present invention removes such a defect source via two methods. One is to directly remove the defect source using a photoresist pattern exposing thereof. The other is to fix the defect source in place in the wafer edge region by protecting thereof by a photoresist pattern during subsequent cleaning processes.

Method of processing a defect source at a wafer edge region in a semiconductor manufacturing

Methods of fabricating semiconductor devices having protected plug contacts and upper interconnections

The present invention relates to a method and composition of an oral preparation of itraconazole, an excellent azole antifungal drug. More particularly, it relates to an oral preparation of itraconazole having improved bioavailability, which is prepared by following steps of: i) dissolving itraconazole and bydrophilic polymer with solvent, ii) spray-drying said mixture, and iii) preparing the solid dispersions for oral preparation. The solid dispersions prepared in this invention may be useful in preparing tablets, granules and other oral dosage forms.

Method and composition of an oral preparation of itraconazole

A method of manufacturing a DRAM device comprises forming a bit line interlayer insulating layer over a substrate over which a bit line pattern is formed; planarizing the bit line interlayer insulating layer; forming enlarged grooves exposing a conductive layer of the bit line pattern; forming bit lines; forming a silicon nitride layer over the substrate; forming a silicon nitride pattern having silicon nitride spacers formed on side walls of the enlarged grooves positioned on the conductive layer; forming the bit lines at the enlarged width portions of the bit line pattern; forming storage node contacts, storage nodes, a dielectric layer, and plate electrodes at a cell area; forming a wiring interlayer insulating layer on the substrate; forming metal contact holes; and forming plugs filling the metal contact holes.

Method of manufacturing DRAM device invention

A method of fabricating a capacitor storage node having HSG silicon on inner walls thereof, wherein the HSG silicon is formed on the inner walls of the storage node after a sacrificial insulating layer is removed, thereby increasing overall surface area of the storage node and preventing electrical bridges between adjacent storage nodes. The storage node is made of a double layer including a layer of crystallized silicon and a layer of amorphous silicon, formed in a storage opening that is formed in the sacrificial insulating layer. The crystallized silicon defines outer walls of the storage node and the amorphous silicon defines inner walls. After forming the storage node opening in the sacrificial insulating layer, crystallized silicon is formed in the opening. Amorphous silicon is then formed on the crystallized silicon. After removing the sacrificial insulating layer, HSG silicon is formed on the amorphous silicon layer.

Method of fabricating a cylindrical capacitor storage node having HSG silicon on inner wall thereof in a semiconductor device

A self aligned contact (SAC) pad in a semiconductor device and a method for forming thereof wherein an SAC opening is formed concurrently with single-layer gate spacers. After formation of the stacked gate pattern having a gate electrode and a capping layer disposed thereon, an insulating layer for gate spacers is deposited thereon. An interlayer insulating layer then is deposited over the insulating layer. The interlayer insulating layer has an etch selectivity with respect to the capping layer and insulating layer. SAC then are opened in the interlayer insulating layer while concurrently forming single-layer gate spacers.

Method for forming a self aligned contact in a semiconductor device

Integrated circuit contact holes may be formed on an integrated circuit substrate, by providing a first conductive pattern on the substrate, a first interlayer insulating film on the first conductive pattern, a second conductive pattern on the first interlayer insulating film and a second interlayer insulating film on the second conductive pattern. A blocking layer pattern is formed on the second interlayer insulating film. The blocking layer pattern overlies, is of the same pattern as, and is as least as wide as the second conductive pattern. The first and second interlayer insulating films are then selectively etched relative to the blocking layer pattern and the second conductive pattern, to form contact holes that expose the first conductive pattern. A photoresist pattern may also be formed on a portion of the blocking layer pattern. Then, the first and second interlayer insulating films are selectively etched relative to the photoresist pattern, the blocking layer pattern and the second conductive pattern, to form contact holes that expose the first conductive pattern. The above-described integrated circuit contact hole forming methods may also be used to form integrated circuit contact holes for integrated circuit memory devices. For integrated circuit memory devices, the first conductive pattern may correspond to pad electrodes, the second conductive pattern may correspond to bit lines, and capacitor contact plugs may be formed in the contact holes.

Methods of forming integrated circuit contact holes using blocking layer patterns

A method for fabricating a Dynamic Random Access Memory (DRAM) device includes the steps of forming a word line on a substrate, forming a first insulating layer on the substrate and on the word line, forming a bit line the first insulating layer, and forming a second insulating layer on the first insulating layer and on the bit line. A sacrificial layer is formed on the second insulating layer, and a contact hole is formed through the sacrificial layer, and the first and second insulating layers. A conductive plug is formed in the contact hole, and the sacrificial layer is removed thereby exposing upper side portions of the conductive plug to define a capacitor electrode.

Methods for forming electrodes including sacrificial layers

A method of manufacturing an active matrix LCD is disclosed whereby gate bus lines, gate electrodes and source bus line segments are patterned from the same vacuum deposited first metal layer. An insulating layer, semiconductor layer, extrinsic semiconductor layer and second metal layer are then successively deposited on the substrate. A TFT channel region is formed by etching each of these layers in a second patterning process. During this step, storage capacitors may be formed by patterning the second metal layer so that it overlaps part of the gate bus lines. A transparent conductive layer is next deposited on the substrate. Pixel electrodes are then formed by patterning the transparent conductive layer in a third patterning process. Further, using a portion of the transparent conductive layer as a mask, the second metal layer and part of the extrinsic semiconductor layer are etched to form source and drain electrodes. Additionally, the transparent conductive layer can be patterned to provide an electrical connection between adjacent bus line segments to form a plurality of electrically continuous source bus lines.

Growing community of inventors

Kyunggi-do, South Korea

Kyu-Hyun Lee