International Business Machines Corporation

Kyu-Hyoun Kim

Warren Edward Maule

Jimmy Grant Foster, Sr

Paul William Coteus

Daniel Mark Dreps

Kevin Charles Gower

Hillery C Hunter

Charles Arthur Kilmer

George L Chiu

Seyoung Kim

Edgar Rolando Cordero

Chia-Yu Chen

Stephen P Glancy

Kevin M Mcilvain

Mingu Kang

A method and/or system for checking the bus/interface between a host and a memory system during memory access operations includes a memory system having one or more of the data memory devices and a spare memory device; providing a bus/interface between a host and the memory system; selecting information on a per memory device basis to associate with a spare memory device; disassociating the selected information from the one or more data memory devices and associating the selected information with the spare memory device; adding Cyclical Redundancy Check (CRC) code to the one or more data memory devices from which the selected information was disassociated; transferring the CRC code and information over the bus and interface between the host and the memory system; and checking the bus interface with the CRC code added to the one or more data memory devices.

Method and apparatus to reduce bandwidth overhead of CRC protection on a memory channel

A computer-implemented method for improving the efficiency of computing an activation function in a neural network system includes initializing, by a controller, weights in a weight vector associated with the neural network system. Further, the method includes receiving, by the controller, an input vector of input values for computing a dot product with the weight vector for the activation function, which determines an output value of a node in the neural network system. The method further includes predicting, by a rectifier linear unit (ReLU), which computes the activation function, that the output value of the node will be negative based on computing an intermediate value for computing the dot product, and based on a magnitude of the intermediate value exceeding a precomputed threshold value. Further, the method includes, in response to the prediction, terminating, by the ReLU, the computation of the dot product, and outputting a 0 as the output value.

Activation function computation for neural networks

An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.

Advanced memory device having improved performance, reduced power and increased reliability

An integrated circuit die stack including a first integrated circuit die mounted upon a substrate, the first die including pass-through vias ('PTVs') composed of conductive pathways through the first die with no connection to any circuitry on the first die; and a second integrated circuit die, identical to the first die, rotated with respect to the first die and mounted upon the first die, with the PTVs in the first die connecting signal lines from the substrate through the first die to through silicon vias ('TSVs') in the second die composed of conductive pathways through the second die connected to electronic circuitry on the second die; with the TSVs and PTVs disposed upon each identical die so that the positions of the TSVs and PTVs on each identical die are rotationally symmetrical with respect to the TSVs and PTVs on the other identical die.

Integrated circuit die stacks with rotationally symmetric vias

Integrated circuit die stacks having a first die mounted upon a substrate, the first die manufactured to be initially identical to a second die with a plurality of through silicon vias ('TSVs'), the first die personalized by blowing fuses on the first die, converting the TSVs previously connected through the blown fuses into pass-through vias ('PTVs'), each PTV implementing a conductive pathway through the first die with no connection to any circuitry on the first die; and the second die, manufactured to be initially identical to the first die and later personalized by blowing fuses on the second die, the second die mounted upon the first die so that the PTVs in the first die connect signal lines from the substrate through the first die to TSVs in the second die.

Integrated circuit die stacks having initially identical dies personalized with fuses and methods of manufacturing the same

Integrated circuit die stacks having a first die mounted upon a substrate, the first die manufactured to be initially identical to a second die with a plurality of through silicon vias ('TSVs'), the first die personalized by opening switches on the first die, converting the TSVs previously connected through the open switches into pass-through vias ('PTVs'), each PTV implementing a conductive pathway through the first die with no connection to any circuitry on the first die; and the second die, manufactured to be initially identical to the first die and later personalized by opening switches on the second die, the second die mounted upon the first die so that the PTVs in the first die connect signal lines from the substrate through the first die to TSVs in the second die.

Integrated circuit die stacks having initially identical dies personalized with switches and methods of making the same

An integrated circuit die stack including a first integrated circuit die mounted upon a substrate, the first die including pass-through vias ('PTVs') composed of conductive pathways through the first die with no connection to any circuitry on the first die; and a second integrated circuit die, identical to the first die, shifted in position with respect to the first die and mounted upon the first die, with the PTVs in the first die connecting signal lines from the substrate through the first die to through silicon vias ('TSVs') in the second die composed of conductive pathways through the second die connected to electronic circuitry on the second die; with the TSVs and PTVs disposed upon each identical die so that the positions of the TSVs and PTVs on each identical die are translationally compatible with respect to the TSVs and PTVs on the other identical die.

Growing community of inventors

Yorktown Heights, NY, United States of America

Kyu-Hyoun Kim