International Business Machines Corporation

Globalfoundries Inc.

Lenovo (singapore) Pte. Ltd.

Kyu-hyoun Kim

Warren Edward Maule

Hillery C Hunter

Charles Arthur Kilmer

Paul William Coteus

Saravanan Sethuraman

Michael B Healy

Kevin M Mcilvain

Luis Alfonso Lastras-Montano

Daniel Mark Dreps

Michele M Franceschini

Diyanesh B Chinnakkonda Vidyapoornachary

Adam J McPadden

Kevin Charles Gower

Ashish Jagmohan

Edgar Rolando Cordero

Gary A Tressler

Kenneth Lee Wright

Anuwat Saetow

Stephen P Glancy

Joab Daniel Henderson

Moinuddin K Qureshi

Glen Arthur Wiedemeier

Brian John Connolly

Mingu Kang

Jimmy Grant Foster, Sr

Jeffrey A Sabrowski

Seyoung Kim

John Kenneth DeBrosse

Robert Brett Tremaine

Michael Anthony Sorna

Rona Yaari

Vipin Patel

Todd Edward Takken

Douglas James Joseph

Anil Bindu Lingambudi

Ankur Agrawal

Luis A Lastras

Janani Mukundan

Michael Kevin Kerr

Saurabh Chadha

James A Mossman

Abhijit Saurabh

William M Zevin

David William Mann

Vipinchandra Patel

Monodeep Kar

Nandita A Mitra

Chung H Lam

Patrick James Meaney

Frank David Ferraiolo

Timothy Jay Dell

William Vincent Huott

James A O'Connor

Thomas Mario Cipolla

Chia-Yu Chen

Shawn Anthony Hall

Barry Marshall Trager

Edmund D Blackshear

David D Cadigan

SangBum Kim

Paul William Rudrud

Dustin James VanStee

Eun Kyung Lee

Diyanesh B Vidyapoornachary

Andrea Fasoli

Philip Jacob

Jacob D Sloat

Seonghoon Woo

Techniques for performing analog-to-digital conversion are described. For example, a method performs an analog-to-digital conversion of an analog input to a digital output including a set of bits, the set of bits including a most significant bit and one or more additional bits, the analog-to-digital conversion starting at a given one of the one or more additional bits following the most significant bit.

Analog-to-digital conversion with bit skipping functionality

An apparatus includes multiple analog to digital converters. Individual analog to digital converters are configured to produce a digital output from an analog input and configured to compute a least significant bit of the digital output by comparing an internal residual voltage for determination of the least significant bit and a residual voltage from another analog to digital converter.

Stochastic rounding switched capacitor computation cores useful for efficient deep learning inference

Mixed signal multipliers and methods for operating the same include a sampling capacitor and an accumulate capacitor. A sampling switch is configured to store an analog value on the sampling capacitor when a digital bit value of a digital signal is one and to store a zero when the digital bit value of the digital signal is a zero. An accumulate switch is configured to store an average of the stored value of the sampling capacitor and a previous stored value of the accumulate capacitor. A processor is configured to alternately trigger the sampling capacitor and the sampling capacitor for each bit value in the digital signal.

Dual capacitor mixed signal mutiplier

An apparatus comprises at least one processor and at least one memory including instruction code configured to, with the at least one processor, cause the apparatus at least to perform a successive approximation analog-to-digital conversion of an analog input, representing a result of multiplication of first and second vectors, to a digital output by determining an upper bound on the result of multiplication of the first and second vectors, identifying, based at least in part on the determined upper bound, at least a portion of the successive approximation analog-to-digital conversion to be skipped, and skipping the identified portion of the successive approximation analog-to-digital conversion.

Energy-efficient analog-to-digital conversion in mixed signal circuitry

A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.

Efficient and selective sparing of bits in memory systems

A memory system for storing data that includes providing a memory module having one or more memory devices and a voltage regulator for controlling voltage levels supplied to the one or more memory devices, wherein the voltage regulator has a first state that permits write and read operations with the one or more memory devices, and a second state where the voltage regulator prevents at least read operations with the one or more memory devices the system configured to store an encryption key in ROM on the voltage regulator; copy the encryption key value from the ROM to a voltage regulator register; set a voltage regulator encryption timer for a period of time; and transition the voltage regulator to the second state in response to the voltage regulator encryption timer expiring.

Method and apparatus for securing memory modules

A card, e.g. a printed circuit board (PCB), has one or more conductive layers and one or more non-conductive layers disposed and alternating upon one another to form a stack. One or more of the conductive layers has one or more wiring elements within the conductive layer. The PCB/card has one or more card edges. The PCB also has a plurality of dual-level pad structures on each of one or more of the card edges. The dual-level pad structures each have an upper level, a lower level, and two or more walls. The lower level is a conductive pad with conductive surface. At least one of the conductive pads electrically connects to one or more of the wiring elements and/or one or more vias. In each of the dual-level pad structures, the walls and upper level may be made of an electrically non-conductive, insulating, or dielectric material or may be covered with a conductive material that electrically connects to conductive surface. There are different non-limiting embodiments of the structures and methods of making the structures.

Dual-level pad card edge self-guide and alignment of connector

A system is provided for error resiliency in a bit serial computation. A delay monitor enforces an overall processing duration threshold for bit-serial processing all iterations for the bit serial computation, while determining a threshold for processing each iteration. At least some iterations correspond to a respective bit in an input bit sequence. A clock generator generates a clock signal for controlling a performance of the iterations. Each of iteration units perform a particular iteration, starting with a Most Significant Bit (MSB) of the input bit sequence and continuing in descending bit significant order, and by selectively increasing the threshold for at least one iteration while skipping from processing at least one subsequent iteration whose iteration-level processing duration exceeds a remaining amount of an overall processing duration for all iterations, responsive to the at least one iteration requiring more time to complete than a current value of the threshold.

Bit-serial computation with dynamic frequency modulation for error resiliency in neural network

A differential mixed-signal logic processor is provided. The differential mixed-signal logic processor includes a plurality of mixed-signal multiplier branches for multiplication of an analog value A and a N-bit digital value B. Each of the plurality of mixed-signal multiplier branches include a first capacitor connected across a second capacitor and a third capacitor to provide a differential output across the second and third capacitors. A capacitance of the first capacitor is equal to half a capacitance of the second and third capacitors.

Differential mixed signal multiplier with three capacitors

A memory subsystem is disclosed comprising at least one memory module, the memory module having a substrate to which a plurality of memory chips is mounted and a voltage regulator, the voltage regulator receiving a power supply signal from a system power supply and outputting two or more power signals, each power signal providing a different, regulated voltage, which regulated voltages are each routed to each of the memory chips; and a redundant voltage regulator external to and not mounted on the memory module and configured to output two or more power signals, providing external different, regulated voltages which are the same voltages as the voltages output by the voltage regulator on the memory module, and supplying the two or more signals to the memory module.

Redundant voltage regulator for memory devices

A method and/or system for checking the bus/interface between a host and a memory system during memory access operations includes a memory system having one or more of the data memory devices and a spare memory device; providing a bus/interface between a host and the memory system; selecting information on a per memory device basis to associate with a spare memory device; disassociating the selected information from the one or more data memory devices and associating the selected information with the spare memory device; adding Cyclical Redundancy Check (CRC) code to the one or more data memory devices from which the selected information was disassociated; transferring the CRC code and information over the bus and interface between the host and the memory system; and checking the bus interface with the CRC code added to the one or more data memory devices.

Method and apparatus to reduce bandwidth overhead of CRC protection on a memory channel

A technique relates to operating a memory controller. The memory controller drives first memory devices and second memory devices of the memory controller in a dual channel mode. A first error correcting code (ECC) memory device and a second ECC memory device protect the first memory devices and the second memory devices. The memory controller drives the first memory devices and the second memory devices in a single channel mode such that the second ECC memory device is a spare memory device, and the first ECC memory device protects the first memory devices and the second memory devices. The memory controller is configured to switch between the dual channel mode and the single channel mode.

Using dual channel memory as single channel memory with spares

A method of operating a memory controller performing activation of a memory device, the method including determining a selection signal for each tile column in a memory block of the memory device by activating respective local word lines, wherein the block selection signal is determined by performing a radix n operation on a vector identifying elements to be read or written.

Multi-dimensional accesses in memory

Growing community of inventors

Mount Kisco, NY, United States of America

Kyu-hyoun Kim