Samsung Electronics Co., Ltd.

Hyundai Motor Company

Kyu-Chan Lee

Jong-Hyun Choi

Dong-Il Seo

Jai-Hoon Sim

Chul-Woo Yi

Young-Hun Seo

Young-Sun Min

Keum-yong Kim

Nam-jong Kim

Jae-Hoon Kim

Sung-Soo Kim

Hye-Jin Kim

Sang-Seok Kang

Jong-hyun Choi

Byung-chul Kim

Ho-Cheol Lee

Jung-Hwa Lee

Jae-Hun Jeong

Jin-Seok Lee

Ho-seop Lee

Yong-Jun Kim

Dong-min Kim

Hyeong-sik Choi

Seung-Moon Yoo

Tae-jin Kim

Woo-Seop Jeong

Sang-bo Lee

Dong-hyun Sohn

Dong-Hak Shin

Jae-Hoon Joo

Yong-Gyu Chu

Sang-Jae Rhee

Sung-Min Yim

Sang-Kyu Kang

Hyo-Joo Ahn

Myung-Gyoo Won

Jae-Moon Lee

Yun-Young Lee

Chul-woo Yi

Hong-il Yoon

Sang-hyoun Kim

Young-hun Seo

Jong-Dae Kim

Byung-Heon Kwak

Sung-Jin Lim

Min-hoon Lee

Jung-Yong Choi

Gang-mo Koo

Byung-kwan Kim

Sang-Hyun Jang

Jong-Sik Na

Hyoung-Pyo Lee

A MRAM includes a memory cell array of spin-transfer torque magnetic random access memory (STT-MRAM) cells and a source line commonly connected to the plurality of STT-MRAM cells. A source line voltage generator generates a source line driving voltage in response to an external power supply voltage and provides the source line driving voltage to the source line.

Magneto-resistive memory device including source line voltage generator

A display apparatus for calibrating a grayscale data including a timing controller, and a method for driving a panel are provided. A display apparatus includes a timing controller which calibrates the grayscale data of the current frame using the grayscale data of the previous and the current frame and a driving unit which drives a panel using the calibrated grayscale data of the current frame. By generating calibrated grayscale data which are variable according to the change of grayscale, response times of liquid crystal may be improved.

Apparatus and method for calibrating grayscale data using an overdrive method, pre-tilt method, and an undershoot method

A method of outputting temperature data in a semiconductor device and a temperature data output circuit are provided. A pulse signal is generated in response to a booting enable signal activated in response to a power-up signal and the generation is inactivated in response to a mode setting signal during a power-up operation. A comparison signal is generated in response to the pulse signal by comparing a reference voltage independent of temperature with a sense voltage that varies with temperature change. The temperature data is changed in response to the comparison signal. Thus, the temperature data output circuit can rapidly output the exact temperature of the semiconductor device measured during the power-up operation.

Method of outputting temperature data in semiconductor device and temperature data output circuit therefor

A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors. In this layout structure, each of the plurality of transistors forming the first bit line sense amplifier is arranged so as not to share an active region with any transistors forming the second bit line sense amplifier.

Layout structure of bit line sense amplifiers for a semiconductor memory device

Provided are a semiconductor memory device and a test method thereof. The semiconductor memory device includes: a die in which a plurality of internal circuits are integrated; a plurality of first and second channel pads having a first pad size and a first pad pitch, disposed in an alternating manner in a straight line at a center part of the die, and divided into a plurality of parallel rows, wherein the plurality of first and second channel pads are configured to selectively contact test probes in an alternating manner to receive an external wafer test signal and to output a signal generated by the plurality of internal circuits to the exterior. Therefore, it is possible to perform a test using plural channel pads during a wafer test of the semiconductor memory device using a plurality of probes of a probe card without incorrect contacts or non-contact with adjacent pads.

Semiconductor memory device and test method thereof

A semiconductor memory device includes: a substrate with first and second memory-cell array regions disposed on first and second substrate sides and first and second sense-circuit regions disposed on the first and second substrate sides between the first and second memory-cell array regions; first and second bitlines coupled to a plurality of memory cells in the first memory-cell array region; first and second complementary bitlines coupled to a plurality of memory cells in the second memory-cell array region; first and second column-selection transistors formed in the first sense-circuit region, and selectively couple the first bitline and the first complementary bitline to a first input/output (I/O) line and a first complementary I/O line; and third and fourth column-selection transistors formed in the second sense-circuit region, and selectively couple the second bitline and the second complementary bitline to a second I/O line and a second complementary I/O line.

Semiconductor memory device

A driver circuit for an integrated circuit device includes a transistor that has a gate terminal, a source terminal, and a bulk substrate terminal. The source terminal is connected to the bulk substrate terminal. A pull-up circuit is connected between a power supply node and the source terminal. The pull up circuit is configured to increase a voltage at the source terminal and the bulk substrate terminal of the transistor responsive to a control signal.

Driver circuits for integrated circuit devices that are operable to reduce gate induced drain leakage (GIDL) current in a transistor and methods of operating the same

A reset signal generator includes an output unit, a trip signal generator, an inverter unit, and a variation reducing unit. The output unit generates a reset signal from a pre-reset signal, and the reset signal follows a supply voltage signal before transitioning to a ground level when the supply voltage signal reaches a tripping voltage. The variation reducing unit is coupled to the inverter unit for reducing a range of the tripping voltage with temperature variations.

Reset signal generator in semiconductor device

An internal reference voltage generating circuit that reduces a standby current and the number of pins of a semiconductor memory device, in which a reference voltage is provided to an input buffer that receives a signal through an input to which an on die transmitor resistor is connected, includes: a voltage dividing circuit outputting the reference voltage by a power voltage; a pull down driver connected to an end of the voltage dividing circuit; and a calibration control circuit comparing a voltage level of the input and a voltage level of an end of the voltage dividing circuit, and controlling the on resistor value of the pull down driver according to a result of the comparison. The internal reference voltage generating circuit is operated while the memory controller inputs a signal into a mode register set (MRS) to enable the internal reference voltage generating circuit and the output signal of the MRS is activated.

Internal reference voltage generating circuit for reducing standby current and semiconductor memory device including the same

A dynamic random access memory (DRAM) device, including a DRAM core having memory cells for storing data information, and a read protection unit, prevents data stored in the memory cells before power-off, from being read out at power-on.

Methods and devices for preventing data stored in memory from being read out

An inrush current prevention circuit for a DC-DC converter is provided and in preferred aspects comprises a switching element that transforms an input voltage by being switched on and off and outputs the transformed voltage. A filter filtrates the outputted voltage, transformed via the switching element, and outputs the filtrated voltage as an output voltage. A reference voltage generator generates a reference voltage. An error amplifier compares the reference voltage and output voltage and outputs an error signal. A Pulse Width Modulation (PWM) signal generator generates a PWM signal to switch on and off the switching element according to the error signal. An on-off circuit either transmits or isolates the PWM signal to the switching element. An Electronic Control Unit (ECU) controls the on-off circuit. Preferred systems of the invention can prevent an inrush current immediately following power input or during reactivation of the DC-DC converter.

Inrush current prevention circuit for DC-DC converter

An external high/low voltage compatible semiconductor memory device includes an internal voltage pad, an internal voltage generation circuit, and an internal voltage control signal generation circuit. The internal voltage pad connects a low external voltage with an internal voltage, and the internal voltage generation circuit generates an internal voltage in response to an internal voltage control signal and a high external voltage. The internal voltage control signal generation circuit generates an internal voltage control signal according to an high or low external voltage. Thus, a database of the semiconductor memory device can be managed without classifying the database into databases for the high voltage and databases for the low voltage because of the internal voltage control signal. In addition, the internal voltage level is stable because charges provided to the internal voltage are regulated according to a voltage level of the external voltage.

Semiconductor memory device having an internal voltage generation circuit for selectively generating an internal voltage according to an external voltage level

A bit line pre-charge circuit of a semiconductor memory device includes a pre-charge circuit connected between a pair of bit lines for pre-charging the pair of bit lines in response to a pre-charge control signal and a pre-charge voltage transmitting circuit for transmitting a pre-charge voltage to the pre-charge circuit in response to the pre-charge control signal. A voltage drop in a pre-charge voltage generation line may be prevented when a short circuit is formed between a word line and a pair of bit lines, and current consumption during a standby operation of the semiconductor memory device may also be reduced, by preventing current from flowing from the pair of bit lines to the pre-charge voltage generation line.

Bit line pre-charge circuit of semiconductor memory device

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Seoul, South Korea

Kyu-Chan Lee