Samsung Electronics Co., Ltd.

Kyoungsub Shin

Ha-Na Kim

Daehyun Jang

Jung-Ik Oh

Sangwuk Park

Kye Hyun Baek

Brad H Lee

Provided is a staircase-shaped connection structure of a three-dimensional semiconductor device. The device includes an electrode structure on a substrate, the electrode structure including an upper staircase region, a lower staircase region, and a buffer region therebetween. The electrode structure includes horizontal electrodes sequentially stacked on the substrate, the horizontal electrodes include a plurality of pad regions constituting a staircase structure of each of the upper and lower staircase regions, and the buffer region has a width that is larger than that of each of the pad regions.

Methods of forming staircase-shaped connection structures of three-dimensional semiconductor devices

Staircase-shaped connection structures of three-dimensional semiconductor devices

Methods for optimizing a plasma process are provided. The method may include obtaining a measurement spectrum from a plasma reaction in a chamber, calculating a normalized measurement standard and a normalized measurement spectrum of the measurement spectrum, comparing the normalized measurement spectrum with a normalized reference spectrum, and comparing the normalized measurement standard with a normalized reference standard to determine whether to change a process parameter of the plasma process or clean the chamber when the normalized measurement spectrum and the normalized reference spectrum are mismatched.

Methods for optimizing a plasma process

Growing community of inventors

Seongnam-si, South Korea

Kyoungsub Shin