Samsung Electronics Co., Ltd.

Kyoungmook Lim

Kwanho Kim

Heungkyu Kwon

Jaehong Park

Seong Woon Kim

Jachun Ku

Kyungheon Noh

Sehwoong Jeong

Jae-Deok Nam

EuiJin Kwon

Youngduck Kim

According to example embodiments, a semiconductor package includes a first and a second semiconductor package. The first semiconductor package includes a first package substrate, first and second memory chips spaced apart from each other on the first package substrate in a first direction, third and fourth memory chips on the first and second memory chips, respectively, and first and second jumper chips on the first and second memory chips, respectively. The first and second jumper chips are spaced apart from the third and fourth memory chips, respectively, in a second direction crossing the first direction. The second semiconductor package may include a second package substrate and a logic chip on the second package substrate. The first semiconductor package may be on the second semiconductor package.

Semiconductor package including stacked memory chips

Disclosed is a level shifter that includes an input node; first and second voltage shifter circuits configured to generate an output clock of a second voltage domain in response to an input clock of a first voltage domain input via the input node, and an output node configured to output the output clock, wherein the first and second voltage shifter circuits have the same structure and are connected in parallel between the input node and an output node.

Level shifter, system-on-chip including the same, and multimedia device including the same

A method of encoding/decoding data for storage and retrieval from a flash memory device, by generating a first error correction code on a combination of first user data to be stored in a first logical unit of storage in the flash memory device and padding data derived from second user data and an associated second error correction code stored in a second logical unit of storage in the flash memory device. The first user data and the first error correction code can be stored in the first logical unit of storage.

Methods of encoding/decoding for error correction code utilizing interdependent portions of codewords and related circuits

A semiconductor memory device is provided. The semiconductor memory device includes an error correction code block and a memory. The error correction code block performs error correction encoding for user data to generate parity data. The memory stores the user data and the parity data. The error correction code block generates parity data, including a number of bits equal to at least 2t, wherein t is a natural number, and the bits of the parity data distinguish free page data from user data that is equal to the free page data.

Semiconductor memory device and data processing method thereof

In the method and apparatus for reverse play, the forward predictive encoded pictures in a compressed video stream are decoded, and selected ones of the decoded, forward predictive encoded pictures are re-encoded as anchor pictures. These anchor pictures are then used to decode portions of the compressed video stream for display in a reverse display order.

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Hwaseong-si, South Korea

Kyoungmook Lim