Samsung Electronics Co., Ltd.

Kyoungmin Kim

Sangwook Park

Dongwook Han

Donggeon Kim

Inseok Baek

Bokyeon Won

Myeongsik Ryu

Seokjae Lee

Youngjin Kim

Jinyong Park

Sukun Yoon

Hyunyong Choi

Sungyong Park

Junsik Choi

Jina Kwon

Yongwoo Shin

Geunsam Yang

Eunjoo Cho

Jungyon Cho

Jungrae Kim

Daesik Yoon

Seungyeon Jeong

Kangil Chung

Hayeon Kil

Daegyu Bae

Siyoung Park

Joon Soo Han

Bok-Yeon Won

Sungho Jang

Ilgweon Kim

Taesung Kang

Youngkyu Lee

A memory device includes a first sub wordline driver including a first active region connected to a first wordline through a first direct contact, and a first transistor connected to a first gate line, the first gate line and the first wordline extending in a first direction, and a second sub wordline driver including a second active region connected to a second wordline through a second direct, the second direct contact and first direct contact extending in parallel in a second direction, the second direction being perpendicular to the first direction. A second transistor is connected to a second gate line. The second gate line extends in the first direction. A third wordline driven by a third sub wordline driver is between the first wordline and the second wordline.

Memory device having sub wordline driver

A memory device includes a memory cell array, a row address decoder configured to generate a plurality of main word line driving signals and a plurality of sub word line driving signals, based on an odd signal representing that a main word line driving signal driving an odd word line is activated, generate a plurality of encoded sub word line driving signals used for driving a target word line by outputting the plurality of sub word line driving signals in a first order, and, based on an even signal representing that a main word line driving signal driving an even word line is activated, generate the plurality of encoded sub word line driving signals by outputting the plurality of sub word line driving signals in a second order, and a word line driving circuit configured to drive the target word line at a first voltage level or a second voltage level.

Memory device including sub word line driving circuit

A sub word-line driver circuit of a semiconductor memory device includes a first active pattern and a second active pattern in a substrate, and a gate pattern. The first active pattern includes a first drain region and a first source region of a first keeping transistor that precharges a first word-line which is inactive and extends in a first direction with a negative voltage. The second active pattern includes a second drain region and a second source region of a second keeping transistor that precharges a second word-line which is inactive and extends in the first direction with the negative voltage. The gate pattern is on a portion of the first active pattern and on a portion of the second active pattern, partially overlaps the first active pattern and the second active pattern.

Sub word-line driver circuit of semiconductor memory device and semiconductor memory device including the same

A sub-word-line driver and semiconductor memory devices including the same are provided. The sub-word-line driver may include a word line pull-up transistor, a word line pull-down transistor, and a keeping transistor configured to maintain a word line at a specified voltage level. The sub-word-line driver may include a peripheral active region on a substrate, a first peripheral gate electrode that corresponds to a gate node of the word line pull-down transistor on the peripheral active region, a second peripheral gate electrode that corresponds to a gate node of the keeping transistor on the peripheral active region, and a first lower contact coupled to a first region of the peripheral active region. A first (VBB) voltage from the first region may be supplied to a source node of the keeping transistor.

Sub-word-line drivers and semiconductor memory devices including the same

The present disclosure relates to a display device, a user terminal device, a method for controlling a display device, and a method for controlling a user terminal device. The disclosure relates to a method in which a display device outputs content that is being output via a user terminal device based on a content request event associated with a request for the display device to output information associated with content that is being output via the user terminal device.

Display device, user terminal device, method for controlling display device, and method for controlling user terminal device

A display device and a method capable of rotating a display based on a type of a user command are provided. The display device according to the disclosure receives a user command while first content is displayed on the display, the display being configured to operate in a first orientation while displaying the first content, maintains the display to operate in the first orientation when the received user command is a command to control a feature corresponding to the first content, determines, based on a type of a second content, to control the display to operate in the first orientation or a second orientation different from the first orientation when the received user command is a command to display the second content on the display, and controls the motor to rotate the display based on the determined first orientation or the second orientation.

Display device and controlling method of display device

An integrated circuit device includes a sense amplifier configured to sense a voltage change of a bit line, wherein the sense amplifier includes: a sense amplifier unit connected to the bit line and a complementary bit line, configured to sense the voltage change of the bit line in response to a control signal, configured to adjust voltages of a sensing bit line and a complementary sensing bit line based on the sensed voltage change, and including a first PMOS transistor and a first NMOS transistor; and a first offset canceling unit connecting the bit line to the complementary sensing bit line in response to an offset canceling signal, and including a first offset canceling transistor arranged between the first NMOS transistor and the first PMOS transistor, wherein the first offset canceling transistor shares a common impurity region with the first NMOS transistor.

Integrated circuit devices

Growing community of inventors

Suwon-si, South Korea

Kyoungmin Kim