Samsung Electronics Co., Ltd.

Korea University Research and Business Foundation

Korea Advanced Institute of Science and Technology

Industry-University Cooperation Foundation Hanyang University

Kyoungho Kim

Jungsik Park

Chulwoo Kim

Yongyoun Kim

Sunghyup Lee

Hyunsu Park

Hoon Moo Choi

Hyoseok Na

Seunghoon Lee

Seok Hwan Kim

Yongseok Lee

Sangmin Kim

Kee-Won Kwon

Seungki Choi

Changsik Yoo

Heeseok Jung

Junhan Bae

Youngsoo Sohn

Jung Hoon Chun

Myungjin Kang

Dongryeol Oh

Baekjin Lim

Jincheol Sim

Jin-Cheol Sim

Jongwook Choi

Kihun Lee

Hanjun Yi

Hyeonjun Jeon

Seungtak Ryu

Pyongil Cho

Eungjin Kim

A semiconductor device includes a multilevel receiver including a signal determiner receiving a plurality of multilevel signals and outputting a result of mutual comparison of the plurality of multilevel signals as an N-bit signal, where N is a natural number equal to or greater than 2. A decoder restores a valid signal among the N-bit signals from the signal determiner to an M-bit data signal, where M is a natural number less than N. A clock generator receives a reference clock signal, generates an input clock signal using the reference clock signal, inputs the input clock signal to the signal determiner, and determines a phase of the input clock signal based on an occurrence probability of an invalid signal not restored to the M-bit data signal among the N-bit signals.

Semiconductor device and memory system

An electronic device comprises: a front housing including a display on a front surface; a rear housing located on a rear surface of the front housing; an antenna clip coupled to the rear housing, wherein the antenna clip may comprise: a coupling body coupled to one end of the rear housing; a first contact portion extending from the coupling body and electrically connected to an external radiator, and a second contact portion electrically connected to a circuit board between the front housing and the rear housing. Other various embodiments may be possible.

Antenna clip and electronic device comprising same

A substrate processing system includes manufacturing process equipment including a plurality of process chambers and a control server configured to control the manufacturing process equipment. When a transporting order of semiconductor substrates is transmitted from the control server to the manufacturing process equipment, the control server provides, to the manufacturing process equipment performing an Nth process cycle (where N is a natural number) in a first transporting order, a command to switch to a second transporting order from an N+1th process cycle immediately when a restriction on at least one process chamber, into which insertion of the semiconductor substrate is restricted, is lifted.

Substrate processing system and substrate processing apparatus

A signal receiver includes a data sampler receiving a differential input signal having first and second input signals and determining bit values of the differential input signal based on first and second reference voltages, and a reference voltage generator performing a pre-tuning operation and a post-tuning operation to generate the reference voltages. The reference voltage generator performs the pre-tuning operation by generating first and second initial voltages and adjusting one of the initial voltages to generate third and fourth voltages. After the pre-tuning operation, the reference voltage generator performs the post-tuning operation by increasing or decreasing the third voltage to generate the first reference voltage and decreasing or increasing the fourth voltage to generate the second reference voltage based on a comparison result between the third voltage and the first input signal and a second comparison result between the fourth voltage and second input signal.

Signal receiver and operation method thereof

A data transmitting and receiving system includes a first device including an encoder configured to encode row data to generate precoding data and a transmitter configured to transmit the precoding data through a transmission channel and a second device including an integrator configured to perform an integral on the precoding data, an integral sampler including a plurality of samplers configured to output sampling data based on an offset value and an output value of the integrator, a decoder configured to decode outputs of some of the samplers to generate decoded data, and a phase detector configured to detect a phase difference between the precoding data and a clock based on the decoded data and an output of another one of the samplers.

Data transmitting and receiving system including clock and data recovery device and operating method of the data transmitting and receiving system

An analog-digital converter includes a first analog-digital conversion unit configured to, during a first analog-digital conversion operation, sequentially charge each of n first differential node pairs, in response to a respective one of a differential sampling signal pair and first to (n&#x2212;1)differential signal pairs among n differential signal pairs, in response to each of the n first differential node pairs being sequentially charged, sequentially generate each of n first differential data pairs, and sequentially generate each of n upper differential data pairs to be used as n-bit upper digital data, in response to a respective one of the sequentially-generated n first differential data pairs. The first analog-digital conversion unit is further configured to, during a second analog-digital conversion operation, simultaneously discharge each of the n first differential node pairs, in response to a ndifferential signal pair among the n differential signal pairs.

Analog-digital converter and semiconductor memory device having the same

Disclosed is an electronic device which includes a housing that includes a first plate, a second plate facing away from the first plate, and a side member surrounding a space between the first plate and the second plate, wherein the side member includes a first conductive portion including a first end and being elongated, a second conductive portion including a second end and a third end and being elongated, the second end being adjacent to the first end, a third conductive portion including a fourth end adjacent to the third end and being elongated, a first insulating portion disposed between the first end and the second end to contact the first end and the second end, and a second insulating portion disposed between the third end and the fourth end to contact the third end and the fourth end, a display that is exposed through the first plate, at least one wireless communication circuit that is electrically connected with a first point placed at the first conductive portion and adjacent to the first end, a first switching element electrically connected with a second point, which is placed at the second conductive portion and is adjacent to the third end, through a capacitive element and electrically connected with a third point placed at the second conductive portion and adjacent to the third end, and a fourth point placed at the third conductive portion and adjacent to the fourth end, at least one ground member that is electrically connected with a fifth point placed at the first conductive portion and more distant from the first end than the first point, a second switching element electrically connected with a sixth point placed at the second conductive portion and adjacent to the second end, a seventh point placed at the second conductive portion and adjacent to the third point, and an eighth point placed at the third conductive portion and more distant from the fourth end than the fourth point, and a control circuit that is configured to control the first switching element and the second switching element. Moreover, various embodiment found through the present disclosure are possible.

Electronic device comprising antenna and method for transmitting or receiving signal

A method of improving antenna performance and an electronic device configured to improve the antenna performance are provided. The electronic device include: a housing; an antenna located inside the housing or formed as part of the housing; a radio frequency (RF) interface configured to transmit/receive wireless signals via the antenna; a groove formed inside an opening in part of the housing; an electrical connector placed inside the groove; a ground member placed inside the housing; a processor electrically connected to the RF interface and the electrical connector; and a memory electrically connected to the processor. The memory stores instructions which enable the processor to detect an external electrical connector inserted into the electrical connector, and select at least one of a plurality of electrical paths between the RF interface and the ground member, in response to at least part of the inserted external electrical connector. Various embodiments are provided.

Electronic device and method of improving antenna performance thereof

A phase-rotating phase locked loop (PLL) may include first and second loops that share a loop filter and a voltage controlled oscillator in order to perform the operation of a phase-rotating PLL, the first and second loops configured to activate in response to an enable signal. The PLL may further include a phase frequency detection controller configured to provide the enable signal to the first and second loops in response to a transition of a coarse signal that may be applied as a digital code.

Phase-rotating phase locked loop and method of controlling operation thereof

Growing community of inventors

Hwaseong-si, South Korea

Kyoungho Kim