Samsung Electronics Co., Ltd.

Infineon Technologies Ag

Kyoung-Woo Lee

Hong-Jae Shin

Woo-Jin Lee

Ja-hum Ku

Ki-Chul Park

Jong-Sam Kim

Woo-Kyung You

Soo-Geun Lee

Seung-Man Choi

Andrew Tae Kim

Min Huh

Young-Sang Lee

Sun Oo Kim

Soo-Guen Lee

Ki-Chul 425-702 Kunyoung Apt Park

Jae-Hak Kim

A method for fabricating a semiconductor device includes sequentially forming an interlayer insulating layer and a hard mask pattern including a first opening on a substrate including a lower pattern, forming a trench exposing the lower pattern in the interlayer insulating layer using the hard mask pattern, forming a liner layer including a first part formed along sidewalls and a bottom surface of the trench and a second part formed along a top surface of the hard mask pattern, forming a sacrificial pattern exposing the second part of the liner layer in the trench, removing the second part of the liner layer and the hard mask pattern using the sacrificial pattern, and after the removing of the hard mask pattern, removing the sacrificial pattern to expose the first part of the liner layer.

Methods for fabricating semiconductor devices using liner layers to avoid damage to underlying patterns

The semiconductor device includes a fuse structure disposed on a substrate. An interlayer dielectric disposed on the fuse structure. A first contact plug, a second contact plug, and a third contact plug penetrate the interlayer dielectric and wherein each of the first contact plug, the second contact plug and the third contact plug are connected to the fuse structure. A first conductive pattern and a second conductive pattern are disposed on the interlayer dielectric. The first conductive pattern and the second conductive pattern are electrically connected to the first contact plug and second contact plug, respectively.

Semiconductor device and methods of forming the same

Example embodiments relate to semiconductor devices having a single body crack stop structure configured to reduce or prevent crack propagation and/or moisture penetration. A semiconductor substrate according to example embodiments may include an active region and a crack stop region surrounding the active region. Interlayer insulating layers may be sequentially stacked on the semiconductor substrate. The interlayer insulating layers may include first dual damascene patterns and a first opening. The first dual damascene patterns may be formed in the interlayer insulating layers so as to be perpendicular to the surface of the semiconductor substrate while exposing a first portion of the semiconductor substrate. The first opening may be formed in the crack stop region and may extend through the interlayer insulating layers to expose a second portion of the semiconductor substrate. First dual damascene metal wirings may be formed in the first dual damascene patterns and may contact the exposed first portion of the semiconductor substrate. A single body first crack stop structure may be formed in the first opening so as to contact the exposed second portion of the semiconductor substrate.

Semiconductor device having crack stop structure

Copper-based metallization is formed in a trench on an integrated circuit substrate by forming a liner of refractory metal in the trench using physical vapor deposition, forming a copper plating seed layer on the liner using physical vapor deposition and then plating copper on the copper plating seed layer. Prior to plating copper on the copper plating seed layer, the liner and/or copper plating seed layer is stuffed with hydrogen, for example by exposing the liner and/or copper plating seed layer to a hydrogen-containing plasma during and/or after formation of the liner and/or copper plating seed layer. Related structures also are disclosed.

Physical vapor deposition methods for forming hydrogen-stuffed trench liners for copper-based metallization

Methods of forming integrated circuit devices include patterning an electrically insulating layer to support dual-damascene interconnect structures therein. The steps of patterning the electrically insulating layer include using multiple planarization layers having different porosity characteristics. Forming an interconnect structure within an integrated circuit device may include forming an electrically insulating layer on a substrate and forming at least one via hole extending at least partially through the electrically insulating layer. The at least one via hole is filled with a first electrically insulating material having a first porosity. The filled at least one via hole is then covered with a second electrically insulating material layer having a second porosity lower than the first porosity. The second electrically insulating material layer is selectively etched back to expose a first portion of the first electrically insulating material in the at least one via hole. The electrically insulating layer is selectively etched to define a trench therein that exposes a second portion of the first electrically insulating material in the at least one via hole.

Methods of forming dual-damascene interconnect structures on semiconductor substrates using multiple planarization layers having different porosity characteristics

Growing community of inventors

Suwon-si, South Korea

Kyoung-Woo Lee