Samsung Electronics Co., Ltd.

Lg Electronics Inc.

Yonsei University

Kyungwon Ferrite Ind. Co., Ltd.

Kyoung-woo Lee

Soo-geun Lee

Jae-hak Kim

Hong-Jae Shin

Soo-Geun Lee

Jeong-Hoon Ahn

Il-Goo Kim

Ki-chul Park

Won-sang Song

Wan-jae Park

Kyung-Tae Lee

Ja-hum Ku

Ki-Chul Park

Ki-Kwan Park

Sang-rok Hah

Seung-Jin Lee

Yong-Jun Lee

Seung-man Choi

Young-jin Wee

Young-joon Moon

Jae-eon Park

Wan-Jae Park

Mu-Kyeng Jung

Seung-Woo Lee

Young-Bae Kim

Mi-young Kim

Young-min Cheong

Shaofeng Ding

Seong-Il Hahm

Yoon-Hae Kim

In-hwan Kim

Jong-Sam Kim

Hyeok-Sang Oh

Jong-hoon Shin

Seung-hak Yu

Hyo-Jong Lee

Bong-Seok Suh

Tack-don Han

Byung-jun Oh

Woo-Jin Jang

Suk Kyu Chang

Seo-woo Nam

Shin-Dug Kim

Sang-cheol Han

Jun-Jung Kim

Jin-Hyeung Park

Hyo-Seon Lee

Sang-Wook Lim

Jong-woon Lee

Jae-Hwan Kwon

Seung-Cheon Kim

Jeong-Wook Hwang

Sung-Bong Yang

Soo-hwan Kim

Ju-Hyuk Chung

Hyun-choong Kim

Hyoung-jong So

Hong-hee Kim

Suk-Hee Jang

Ho-jung Cha

Yo-han Ko

Jae-yeol Maeng

Il-whan Oh

Sae-il Son

An interposer includes a substrate having a mounting area and a test area, first conductive plugs separate from each other, the first conductive plugs being disposed along a first direction and into the test area of the substrate, a first line pattern group including first non-conductive patterns disposed on first centers of the first conductive plugs, and first conductive patterns disposed to bridge first peripheries of a first adjacent pair of the first conductive plugs, and first pads connected to the first conductive patterns at both first ends of the first line pattern group.

Interposer, method of manufacturing interposer, and method of manufacturing semiconductor package

Disclosed is a system for recognizing a user location using sensor-based activity recognition. The system includes a mobile device which includes a sensor module configured to sense information about at least one of a user state and surrounding environments, a first processor configured to extract activity information based on the sensed information, and a first communication module configured to transmit the extracted activity information; and a user terminal device which includes a second communication module configured to receive the activity information from the first communication module, and a processor configured to determine a user location in a user space corresponding to a user activity based on the received activity information. By determining a user's location in a user space corresponding to a user activity, it is possible to control electronic devices corresponding to the user activity or provide a service of monitoring activities of the old and weak and the child.

User terminal device and method for recognizing user'S location using sensor-based behavior recognition

A wiring structure includes a substrate, a lower insulation layer on the substrate, a lower wiring in the lower insulation layer, a first etch-stop layer covering the lower wiring and including a metallic dielectric material, a second etch-stop layer on the first etch-stop layer and the lower insulation layer, an insulating interlayer on the second etch-stop layer, and a conductive pattern extending through the insulating interlayer, the second etch-stop layer and the first etch-stop layer and electrically connected to the lower wiring.

Wiring structures and semiconductor devices

Disclosed is a monitoring TEG for an etching process in a semiconductor device. The TEG includes an etch stopping layer on a substrate and a target layer to be etched provided on the etch stopping layer. The target layer to be etched includes a first opening portion formed by etching a portion of the target layer to be etched and a second opening portion formed by etching another portion of the target layer to be etched. The second opening portion has a smaller depth than the first opening portion. A depth of a partial contact hole formed by a first partial etching process may be measured.

Monitoring test element groups (TEGs) for etching process and methods of manufacturing a semiconductor device using the same

In a method of forming a wiring structure, a first insulation layer is formed on a substrate, the first insulation layer comprising a group of hydrocarbon (CH) wherein &#x3b1; and &#x3b2; are integers. A second insulation layer is formed on the first insulation layer, the second insulation layer being avoid of the group of hydrocarbon. A first opening is formed through the first and the second insulation layers by etching the first and the second insulation layers. A damaged pattern and a first insulation layer pattern are formed by performing a surface treatment on a portion of the first insulation layer corresponding to an inner sidewall of the first opening. A sacrificial spacer is formed in the first opening on the damaged pattern and on the second insulation layer. A conductive pattern is formed in the first opening. The sacrificial spacer and the damaged pattern are removed to form a first air gap between the conductive pattern and the first insulation layer pattern, and to form a second air gap between the conductive pattern and the second insulation layer.

Methods of forming wiring structures

A wiring structure includes a conductive pattern on a substrate, a first insulation layer pattern between adjacent conductive patterns and a second insulation layer pattern on the first insulation layer pattern. The first insulation layer pattern is separated from the conductive pattern by a first distance to provide a first air gap. The second insulation layer pattern is spaced apart from the conductive pattern by a second distance substantially smaller than the first distance to provide a second air gap. The wiring structure may have a reduced parasitic capacitance while simplifying processes for forming the wiring structure.

Wiring structures

In a method of forming an insulation layer pattern, an insulation layer is formed on a substrate. An organic layer and a hard mask layer are successively formed on the insulation layer. A preliminary hard mask pattern having first openings is formed by patterning the hard mask layer. A hard mask pattern having the first openings and second openings is formed by patterning the preliminary hard mask pattern. Width control spacers are formed on sidewalls of the first and the second openings. An etching mask pattern is formed by etching the organic layer using the hard mask pattern as an etching mask. The insulation layer pattern having third openings is formed by etching the insulation layer using the etching mask pattern as an etching mask.

Methods of forming insulation layer patterns and methods of manufacturing semiconductor devices including insulation layer patterns

Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.

Interconnections having double capping layer and method for forming the same

An actuator to drive a mirror of a holographic information storing apparatus, the actuator including: piezoelectric cells; support members mounted on the piezoelectric cells; a hinge member mounted on the support member; and a post mounted on the hinge member, to support the mirror. The hinge member includes a bar disposed parallel to a rotation axis of the mirror, and a curved portion that extends from the bar.

Actuator for holographic information storing apparatus

Methods of forming CMOS integrated circuit devices include forming at least first, second and third transistors in a semiconductor substrate and then covering the transistors with one or more electrically insulating layers that impart a net stress (tensile or compressive) to channel regions of the transistors. The covering step may include covering the first and second transistors with a first electrically insulating layer having a sufficiently high internal stress characteristic to impart a net tensile (or compressive) stress in a channel region of the first transistor and covering the second and third transistors with a second electrically insulating layer having a sufficiently high internal stress characteristic to impart a net compressive (or tensile) stress in a channel region of the third transistor. A step may then performed to selectively remove a first portion of the second electrically insulating layer extending opposite a gate electrode of the second transistor. In addition, a step may be performed to selectively remove a first portion of the first electrically insulating layer extending opposite a gate electrode of the first transistor and a second portion of the second electrically insulating layer extending opposite a gate electrode of the third transistor.

CMOS integrated circuit devices having stressed NMOS and PMOS channel regions therein

A CMOS integrated circuit has NMOS and PMOS transistors therein and an insulating layer extending on the NMOS transistors. The insulating layer is provided to impart a relatively large tensile stress to the NMOS transistors. In particular, the insulating layer is formed to have a sufficiently high internal stress characteristic that imparts a tensile stress in a range from about 2 gigapascals (2 GPa) to about 4 gigapascals (4 GPa) in the channel regions of the NMOS transistors.

Methods of forming CMOS integrated circuits that utilize insulating layers with high stress characteristics to improve NMOS and PMOS transistor carrier mobilities

Methods for forming an interconnection line and interconnection line structures are disclosed. The method includes forming an interlayer insulating layer on a semiconductor substrate, wherein the interlayer insulating layer is formed of a carbon-doped low-k dielectric layer. An oxidation barrier layer is formed on the interlayer insulating layer. An oxide capping layer is formed on the oxidation barrier layer. A via hole is in the oxide capping layer, the oxidation barrier, and the interlayer insulating layer. A conductive layer pattern is formed within the via hole.

Method for forming interconnection line in semiconductor device and interconnection line structure

A method of forming a dual damascene semiconductor interconnection and an etchant composition specially adapted for stripping a sacrificial layer in a dual damascene fabrication process without profile damage to a dual damascene pattern are provided. The method includes sequentially forming a first etch stop layer, a first intermetal dielectric, a second intermetal dielectric, and a capping layer on a surface of a semiconductor substrate on which a lower metal wiring is formed; etching the first intermetal dielectric, the second intermetal dielectric, and the capping layer to form a via; forming a sacrificial layer within the via; etching the sacrificial layer, the second intermetal dielectric, and the capping layer to form a trench; removing the sacrificial layer remaining around the via using an etchant composition including NHF, HF, HO and a surfactant; and forming an upper metal wiring within the thus formed dual damascene pattern including the via and the trench. The preferred etchant composition for stripping a sacrificial layer in the foregoing dual damascene process consists essentially of NHF, HF, HO and a surfactant.

Method of fabricating dual damascene interconnection and etchant for stripping sacrificial layer

A method for deciding a network manager (NM) in a home network, including the steps of comparing a priority of a current NM and a priority of a new NM when the new NM is plugged-in a home network which is controlled by the current NM and deciding a NM having a higher priority as the NM of the home network between the current NM and the new NM, can smoothly control and manage the home network by deciding a NM having a higher priority as the NM for centralized-controlling the home network.

Method for deciding network manager in home network

Growing community of inventors

Seoul, South Korea

Kyoung-woo Lee