Electronics and Telecommunications Research Institute

Kyoung-Wan Park

Seong-Jae Lee

Min-Cheol Shin

Moon-Gyu Jang

Won-ju Cho

Seong-jae Lee

Seung-Min Park

Young-Jo Ko

Jong-Heon Yang

Woo-Seok Cheong

Sung-Bock Kim

Jeong-Sook Ha

Ki-ju Im

Ji-Hun Oh

Jung-Rae Ro

An ultra small-sized SOI MOSFET having a high integration density, low power consumption, but high performances, and a method of fabricating the same are provided. The method includes preparing a SOI substrate on which a monocrystalline silicon layer is formed, forming a first dielectric material layer doped with impurities of a first conductivity type on the SOI substrate, forming an opening to expose the monocrystalline silicon layer etching at least part of the first dielectric material layer, forming a channel region injecting impurities of a second conductivity type into the monocrystalline silicon layer exposed by the opening, forming a source region and a drain region in the monocrystalline silicon layer diffusing the impurities of the first dielectric material layer using heat treatment, forming a gate dielectric layer in the opening on the channel region, forming a gate electrode on the gate dielectric layer to fit in the opening, forming a second dielectric material layer on the entire surface of the SOI substrate on which the gate electrode is formed, forming contact holes to expose the gate electrode, the source region, and the drain region etching part of the second dielectric material layer, and forming metal interconnections to bury the contact holes.

Ultra small-sized SOI MOSFET and method of fabricating the same

Provided are a Schottky barrier tunnel transistor (SBTT) and a method of fabricating the same. The SBTT includes a buried oxide layer formed on a base substrate layer and having a groove at its upper surface; an ultra-thin silicon-on-insulator (SOI) layer formed across the groove; an insulating layer wrapping the SOI layer on the groove; a gate formed to be wider than the groove on the insulating layer; source and drain regions each positioned at both sides of the gate, the source and drain regions formed of silicide; and a conductive layer for filling the groove. In the SBTT, the SOI layer is formed to an ultra-thin thickness to minimize the occurrence of a leakage current, and a channel in the SOI layer below the gate is completely wrapped by the gate and the conductive layer, thereby improving the operational characteristics of the SBTT.

Schottky barrier tunnel transistor using thin silicon layer on insulator and method for fabricating the same

An apparatus for fabricating silicon thin films for use in laser ablation includes a silicon substrate rotatably mounted in a process chamber maintaining a ultra high vacuum, pulsed light source means mounted outside the process chamber for emitting a pulsed light beam, target rotating means mounted in the process chamber for rotating a plurality of targets mounted therein, the targets being made of a different material, light beam splitting means for splitting the pulsed light beam into double light beams of the same intensity, light beam intensity regulating means for regulating the intensity of the double light beams, wherein the targets are mounted to face the silicon substrate so as to uniformly overlap the vaporization products of the targets generated by irradiating the double light bears on the silicon substrate.

Fabrication method of erbium-doped silicon nano-size dots

A method for fabricating a compound semiconductor substrate having a quantum dot array structure includes the steps of forming a plurality of dielectric thin layer patterns on a substrate, thereby forming an exposed area of the substrate, sequentially forming buffer layers and barrier layers in a pyramid shape on the exposed area of the substrate, forming Ga droplets on the barrier layers, transforming the Ga droplets into GaAs quantum dots, performing a thermal process to the substrate, and growing the buffer layers and the barrier layers to thereby form a passivation layer capping the GaAs quantum dots.

Method for fabricating compound semiconductor substrate having quantum dot array structure

A transistor in accordance with the invention comprises an ultra-thin Mo--C film functioning as a channel for an electron flow with two ends of the thin metal film functioning as source and drain terminals of the transistor, respectively; a piezoelectric film formed on the Mo--C film, for producing a force in accordance with an applied electric field provided by a gate voltage; and an electrode film formed on the piezoelectric film functioning as a gate of the transistor to which the gate voltage is applied to produce the applied electric field; and wherein a resistance of the Mo--C film between the source and drain terminals changes in accordance with the force produced in response to the applied gate voltage. This transistor can be used as an element of the three dimensional integrated circuit with a laminated structure.

Ultra-thin MO-C film transistor

A lateral resonant tunneling transistor having two non-symmetric quantum dots is disclosed. When a negative voltage is supplied to each plurality of thin split gates, two non-symmetric quantum dots are formed owing to the formation of the potential barrier. Thus when a forward bias voltage is applied, the resonant tunneling phenomena occur twice successively. Through these two successive resonant tunneling phenomena and by lowering the height of the third potential barrier 6a, the resonant tunneling current can be maximized.

Lateral resonant tunneling transistor having two non-symmetric quantum

A thin film transistor is disclosed comprising a piezoelectric film formed on a piezoresistive body of an ultra thin film and a gate electrode formed on the piezoelectric film. Due to the force generated from the piezoelectric film by an electric field generated according to the strength of a voltage applied to the gate electrode, a pressure is applied on the piezoresistive body to vary the resistance of the piezoresistive body. Thus, the quantity of current that flows from a source terminal through the piezoresistive channel to a drain terminal can be controlled. Since the piezoresistive body can be formed on a plane, a thin film transistor with a three-dimensional structure can be manufactured.

Thin film transistor with piezoelectric film

Disclosed is the method of producing a piezo-device utilizing an ultra-thin Mo-C film as a piezoresistive material for a general class of improved piezo-device with the high sensitivity and the weak temperature dependence.

Piezoresistive device and fabrication method thereof

A quantum interference device comprises a semi-insulating GaAs substrate; GaAs and AlGaAs layers sequentially formed with high purity on the substrate; a two-dimensional electron gas layer formed in the GaAs layer and serving as a channel; source/drain regions formed on the semi-insulating GaAs substrate and at both ends of a laminated portion composed of the GaAs/AlGaAs layers; and a gate formed on the AlGaAs layer and having a periodic structure wherein the length thereof varies in a periodic manner in a transverse direction. In the device, the electron gas layer formed in the GaAs layer is used as an electron path, and the phases of electrons passing along different electron paths are caused to interfere with each other by the gate, thereby causing the current of a drain therein to be maximized or minimized. The transconductance can be significantly increased.

Growing community of inventors

Daejeon, South Korea

Kyoung-Wan Park